Key Takeaways:

• Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale.
• Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow.
• Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another.

Moore’s Law has shifted toward advanced packaging over the past few years, but the limits of that approach are just now coming into focus.

AI and HPC designs are growing larger and more complex, pushing the next barriers toward package mechanics and process control rather than interconnect density alone. Warpage, glass fragility, hybrid-bond yield, temporary bonding variation, and substrate limitations are becoming increasingly difficult to manage as structures get thinner, larger, and more heterogeneous.

These issues were a recurring theme at this year’s iMAPS conference, and have cropped up in recent interviews, all pointing to the same conclusion — packaging is entering a phase in which mechanical and process-control problems are complicating continued scaling.

That matters because packaging now sits much closer to the center of system performance. It no longer makes sense to talk about the architecture of advanced AI systems as if the package were a passive shell wrapped around the real innovation. Power delivery, thermals, interconnect density, substrate behavior, and process sequence all affect what can be built and what can be manufactured economically.

“What really drives performance today is not really the number of flops, the teraflops, or the petaflops per GPU, but rather the system architecture and the system performance as a whole,” said Sandeep Razdan, director of the Advanced Technology Group at NVIDIA, during his keynote at iMAPS.

Once system architecture becomes the performance driver, packaging stops being a downstream implementation detail and becomes part of the performance equation. The substrate, the carrier, the bonding interface, the thermal path, and even the order in which process steps are performed all matter more.

Those elements are deeply connected. Warpage affects chucking and alignment. Alignment affects bonding yield. Glass can improve flatness and dimensional stability, but it also introduces brittleness and different failure modes. Thinning for backside processing depends on temporary bonding materials, grinding uniformity, and clean debonding. Even substrate shortages are only partly a supply problem. They also reflect broader uncertainty, about which platforms can still scale mechanically, electrically, and economically for advanced AI packages.

Warpage moves to center stage
Warpage may be the most useful place to start, because it sits beneath so many of the other problems. It’s not just a nuisance that shows up late in assembly. More often, it is the visible result of deeper material and structural imbalances built into the stack from the beginning. Those imbalances become more severe as package sizes grow, as more silicon is placed on top of organic materials, and as more layers with different thermal and mechanical behavior are pushed through increasingly complex process flows.

“Panel warpage is fundamentally driven by thermo-mechanical CTE mismatch and stiffness imbalances across the stack,” said Hamed Gholami Derami, strategic technologist for advanced semiconductor packaging at Brewer Science. “There are several different types of polymers with different glass transition temperatures used in the same stack. Going above the Tg (glass transition temperature) of any of these materials causes a sharp drop in modulus and an increase in CTE (coefficient of thermal expansion), which increases warpage. Other factors that affect the panel warpage are layer thickness (direct correlation), cure shrinkage of polymers (causes residual stress and increases warpage), and copper/metal density in the stack (more copper leads to more warpage).”

What this means is advanced packages are no longer relatively simple structures made from a narrow set of materials with reasonably predictable interactions. They are mechanically asymmetrical systems. Different layers expand, soften, shrink, and store stress differently. A stack may seem stable at one temperature and become unstable at another. A cure step that improves one material can distort another. A copper-rich region that improves electrical performance can alter the stiffness balance and increase deformation. This becomes much more consequential when the package gets larger, and the alignment budgets tighten.

“In the packaging world, it’s the worst of all worlds,” said Mike Kelly, vice president, chiplets/FCBGA integration at Amkor. “You start with those organic substrates with high CTE, and then you’re putting lots of low-CTE silicon on top. So it’s imbalanced, and when it heats up it’s going to be anything but flat.”

This is why panel-scale discussions and glass discussions regularly overlap at conferences. As module sizes increase, wafer-scale economics and yield become less compelling, prompting greater interest in panel-scale processing.

“Glass is a totally different material than silicon, with a totally different manufacturing process,” said Lang Lin, principal product manager at Synopsys. “The larger the glass panel you’re trying to make, the more warpage you will see. Today we talk about micrometers of warpage, but with glass it could be even larger. Warpage and residual stress in semiconductor packaging processes involving glass panels are cumulative.”

That concern showed up repeatedly in iMAPS presentations, whether the immediate subject was fan-out, glass carriers, or more advanced die stacking. At larger sizes and finer pitches, a slight bow that once might have been corrected through process adjustment can cascade into alignment problems, handling difficulties, and lower yield.

“We do a certain level of modeling to model the warpage beforehand, and then there are certain levers you can pull to control the warpage,” said Knowlton Olmstead, senior manager in the Wafer Services Business Unit at Amkor. “Some warpage can be tolerated during the assembly process, but if the warpage is too high it can lead to issues.”

Warpage is not merely a simulation output or a materials-science abstraction. At some point, it becomes a simple question of whether the structure can still be held, aligned, and processed repeatably.

Glass solves some problems but creates others
Warpage is one of the big reasons glass keeps surfacing as a panel option in advanced packaging flows. On paper, it offers several attractive properties. It is flat, dimensionally stable, and can be matched much more closely to silicon than many organic materials can. In carrier form, it also creates useful optical options for debonding and alignment.

“Glass is very stable and very level,” said Wiwy Wudjud, engineering program manager at ASE. “It matches very closely to the CTE of silicon wafers. That’s why, using a glass carrier, we can reduce the warpage significantly in the process.”

A flatter structure is easier to bond accurately. A closer thermal match to silicon reduces one of the major sources of stress. For fine-pitch processes, both can directly improve alignment accuracy and process repeatability. Glass also offers transparency, which makes it attractive for optical alignment and for carrier applications that rely on UV or laser debonding.

But glass does not eliminate mechanical problems so much as shift them. While it reduces warpage, it introduces a more brittle material with different failure modes and much less tolerance for mishandling. As glass carriers get larger and are used more extensively in advanced packaging flows, edge damage, chipping, microcracks, and process-induced defects become harder to ignore.

“A glass carrier is no longer an alternative material,” said Wudjud in an iMAPS presentation. “It offers many benefits, but glass is inherently brittle in nature, which introduces reliability concerns, especially cracking and microcracking at the edge of the wafer, which is the weakest point.”

Materials can be flat, stable, and thermally attractive while still failing in ways that are difficult to detect early. Edge damage, microcracks, and cumulative handling defects matter much more when the material has a low tolerance for local damage. The problem becomes even more serious if carriers are reclaimed and reused, because small defects can propagate over time, reducing toughness before a more obvious failure occurs.

ASE focused on that issue in a presentation at iMAPS, emphasizing that edge-related damage in glass is not always captured well by conventional methods. The company even developed a pendulum impact test to evaluate edge toughness under conditions that more closely simulate real handling and packaging stresses.

“The weakest point is at the edge,” said Wudjud. “Failure in brittle materials like glass quickly initiates there, and conventional tests do not fully capture the edge-related damage or real handling conditions.”

Hybrid bonding gets harder as pitch shrinks
Hybrid bonding often gets framed as the next logical step in density scaling, and in many ways it is. It offers the interconnect density and electrical performance needed for tighter die-to-die integration, especially as AI and HPC architectures continue to push for more bandwidth in less space. But the manufacturing challenges are changing as the pitch shrinks. At larger pitches, yield is still heavily influenced by defects and contamination. At smaller pitches, stress begins to dominate in ways that are less visible and often harder to control.

“For pitch sizes above 5 microns, the yield is mostly determined by defects,” said Brewer Science’s Derami. “However, as we shrink the pitch size, we gradually transition to a stress-driven regime, where below a 2 to 3 micron pitch, the yield is primarily stress-driven. This is mostly due to higher copper density at lower pitch sizes, which increases mechanical stress due to copper expansion and dielectric constraints.”

That distinction matters because it changes the dynamics of hybrid bonding. It is still true that contamination and topography control are critical, but once copper density increases and the interface becomes more mechanically constrained, the package can encounter a different class of problems. Stress becomes a part of the dominant failure physics, meaning it is no longer just a secondary concern riding behind cleanliness. As a result, improvements in defect control may no longer be sufficient to maintain yield as pitches continue to shrink.

“Copper hybrid bonding is super sensitive to any kind of particulate contamination because it’s essentially a glass-to-glass interface,” said Kelly. “There are no organics for compliance, so it only takes one nano-sized particle, and you basically lift the glass off and mess up a whole bunch of units on the wafer.”

In a more compliant structure, a small local defect may be partly absorbed or tolerated. In copper hybrid bonding, that tolerance is much lower. The challenge is not only to keep the surfaces clean, but to also manage planarity, oxide and copper topography, annealing behavior, and the mechanical interaction of a denser interconnect structure.

“When you look at the IC architecture side of things, this is where we start to get into hybrid bonding, because it’s required,” said Mark Gerber, group director for IC packaging and product management at Cadence, in a presentation at iMAPS. “You have to have hybrid bonding, and the primary driver for that is the timing considerations. When you’re doing silicon design and integration on the different IP blocks, speed and the timing sensitivity of these is very, very critical.”

Fig. 1: Cadence’s Mark Gerber discusses 3D die/wafer stacking at iMAPS. Source: Gregory Haley/Semiconductor Engineering

Hybrid bonding is not being pursued because it is easy. It is being pursued because more traditional interconnect schemes increasingly fall short in the face of bandwidth, latency, and power demands. As a result, packaging engineers are being pushed toward a process that becomes more sensitive in two directions at once. It remains highly vulnerable to contamination, while also becoming more vulnerable to stress as pitches shrink. The engineering burden is shifting from solving a single dominant problem to solving several tightly coupled problems simultaneously.

That also helps explain why simulation and process co-optimization are taking on a larger role. Companies need to model warpage and stress before manufacturing failures show up in yield, a point that applies especially to hybrid bonding, where small geometric or mechanical variations can propagate into larger integration problems downstream.

Backside handling becomes part of the precision budget
The move toward thinner, denser, higher-performance structures that render hybrid bonding attractive also makes backside handling harder. As dies are thinned more aggressively, the support material beneath them becomes part of the precision budget. Grinding, temporary bonding, debonding, and cleaning are no longer secondary steps that can tolerate broad process variation.

“As devices get thinner, the grinding process becomes more critical and more challenging,” said Derami. “The total thickness variation of the temporary bonding materials directly affects the quality and uniformity of the thinned device and should be low enough to allow for extreme thinning, especially for HBM DRAM dies.”

Temporary bonding materials used to be discussed more as enabling layers, helpful but largely in the background. As device thickness keeps shrinking, that is no longer the case. If the temporary bonding layer varies too much in thickness, the grinding result will vary with it. That variation then affects downstream alignment, mechanical stability, and yield. The carrier and adhesive system are helping to define the precision limits, not simply facilitating the process.

Advanced packaging no longer consists of a series of independent unit processes that can each be optimized in isolation. It is becoming a cumulative mechanical history. Stress introduced in one step affects the margin available in the next. A slight positional shift after one process can narrow alignment tolerance in the next. A warpage problem that seems manageable early can become much harder to correct later, after additional layers and thermal excursions have been added.

“Each step will introduce some kind of stress into the system,” said Synopsys’ Lin. “You have to make sure each step does not create too much stress so the next step can proceed.”

Backside processing offers a clever routing innovation, but it also creates a manufacturing burden. It changes how device structures are supported, cleaned, aligned, and kept intact. Exposed or thinned silicon can help with thermal path design, but it also makes the package more mechanically imbalanced and difficult to manage during later steps.

“With backside power, you put a carrier chip on top because you end up thinning the bulk silicon down to something like five microns,” said Amkor’s Kelly. “You’re almost removing it all, and then you bring power and I/O out the same side, but it’s the opposite side we’re used to.”

Residue and contamination make that burden heavier. Temporary bonding layers can leave residues after debonding, and if cleaning is not done properly, those residues can introduce downstream problems. The physical act of thinning is only part of the challenge. The assembly also has to emerge from the support and debonding sequence clean enough to continue through the rest of the process without adding new yield limiters.

Substrate shortages are really substrate limits
Substrate shortages have been discussed for years as a supply-chain problem, and that remains part of the story, but the issue is now larger than mere availability. Advanced packaging is also pressing against the limits of what traditional substrate platforms can do gracefully as modules grow in size, power, and complexity.

“Everybody’s chasing that technology, but there’s just not enough 200-millimeter substrates around,” said Joe Roybal, senior vice president and general manager of the mainstream business unit at Amkor.

Demand remains high, and capacity does not always line up cleanly with what advanced package programs need. Package size is growing faster than confidence in the mechanical and economic margins of existing approaches.

“As the module size keeps increasing, you cannot fit a lot of units in a wafer, and the cost and the yield numbers don’t make sense at a wafer scale,” said Poulomi Mukherjee, process integration engineer at Applied Materials, in an iMAPS presentation. “If you want to keep up with the demand, we have to move to a higher form factor, which is the panel scale processing.”

Fig. 2: Poulomi Mukherjee of Applied Materials discusses glass substrate challenges. Source: Gregory Haley/iMAPS

That is one reason glass, panel processing, and alternative substrate concepts keep resurfacing in the same conversations. The industry is looking for a platform that can support larger modules, tighter integration, and more difficult thermal and power-delivery requirements without collapsing under its own mechanical complexity. The problem is that each proposed solution solves one class of issues while exposing another. Panel processing may improve economics, but it amplifies warpage and cumulative stress. And backside approaches may improve electrical performance, but they require more aggressive thinning and tight process control.

It is also clear that adoption of new platforms will not be uniform across applications. The enthusiasm around glass at iMAPS was driven largely by AI, HPC, and advanced integration discussions, but that does not mean every market is ready to make the same move. “I don’t see glass happening in automotive,” said Amkor’s Roybal.

Automotive packaging has very different qualification, reliability, and cost expectations than AI accelerators or bleeding-edge HPC modules. In the auto market, proven package types and long-term reliability tend to carry more weight than the promise of a new substrate platform.

Conclusion
The clearest lesson from this year’s packaging discussions is that the next stage of scaling will depend less on any single breakthrough than on whether the whole process stack can be made stable enough to scale. Warpage affects alignment and handling. Handling affects crack formation and edge damage. Thinning affects uniformity, stress, and contamination risk. Hybrid bonding improves density and bandwidth, but it is highly sensitive to both particles and stress as pitch shrinks. What used to look like separate issues are now co-dependent parts of the same manufacturing problem.

The industry’s roadblocks no longer look purely electrical. Engineers certainly can envision more advanced package architectures, creating architectures that can be built repeatably, cleanly, and economically enough to move into sustained production is a challenge. The real constraint is process integration discipline across materials, mechanical behavior, thermal history, and yield management.

That challenge is already reshaping how experts talk about the field. The move to larger modules and tighter die-to-die integration is forcing a more holistic view in which substrate choice, carrier strategy, panel flatness, copper density, debonding cleanliness, and process sequence are all considered together. It is no longer enough to solve one problem locally if the solution creates a larger mechanical penalty two steps later. Scaling increasingly depends on anticipating how the whole structure will behave before the process window closes.

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