Mojo-V (pronounced “mojo-five”) is a new RISC-V extension that introduces privacy-oriented programming capabilities for RISC-V. Mojo-V implements secret computation, enabling secure, efficient, and data-oblivious execution without reliance on fragile software and programmer trust. By sequestering sensitive data in dedicated secret registers and encrypting memory under a third-party key, Mojo-V prevents disclosures and enforces computation that is both blind (no direct disclosures) and silent (no side channel leakage). The design integrates seamlessly into the existing RISC-V ISA with only a mode bit and four new instructions, enforced entirely at decode. Early results show near-native execution speeds while offering over 5-7 orders of magnitude performance improvement compared to fully homomorphic encryption (FHE), with a clear roadmap for integration into CPUs, GPUs, and specialized accelerators.

To learn more...

The current Mojo-V ISA Extension Specification (release 0.91):

To contact the developers of Mojo-V:

The Mojo-V reference platform release 0.91 implements secret integer and floating-point computation using a fixed symmetric key cipher. As of this release, 64-bit secret computation is fully secretized and this early reference platform can be used for software development and red-teaming. Additional capabilities will be rolled out in future releases, including PKI support, LLVM compiler support, 32-bit RISC-V support, VIP-Bench benchmarks support, etc.

Specification Version: 0.91 (October 2025)
Contact: [email protected]

1. Mojo-V ISA Spec v0.91
2. Spike (Instruction Set Simulator) Implementation
   • Mojo-V integrated into riscv-isa-sim, nearly feature-complete
   • Missing only: Public-Key Infrastructure (PKI) support (currently uses fixed keys with a Simon-128 cipher)
   • To run Spike with Mojo-V extensions enabled, add the --isa=rv64gc_zicond_zkmojov_zicntr flag when running spike
3. Mojo-V Bringup-Bench Benchmarks
   • Hand-coded examples (e.g., bubble-sort) showing Mojo-V working secret computation
   • Full battery of security tests for RV64GC+Mojo-V

Note, the remainder of the Bringup-bench benchmarks have NOT been ported to Mojo-V, as yet.

You’ll need an LLVM-based RISC-V cross-compiler capable of producing RV64GC binaries.

Here is a good place to start: https://clang.llvm.org/get_started.html

git clone https://github.com/toddmaustin/mojo-v.git
cd mojo-v

sudo apt-get install device-tree-compiler libboost-regex-dev libboost-system-dev
cd riscv-isa-sim
mkdir build
cd build
../configure --prefix=$RISCV
make

1. Build the Spike device driver

   cd bringup-bench/target
   make

2. Configure your compiler

   Edit ../Makefile and set TARGET_CC for the mojov target to the location of your LVM Clang-based RISC-V compiler.

3. Build and test

   cd ..                # go to the top-level bringup-bench directory
   make mojov-tests     # run all Mojo-V tests

   As an alternative, you can run an individual benchmark by going into its directory and running the following command.

   cd ../mojov-test
   make TARGET=mojov clean build test

All test benchmarks are hand-coded assembly programs demonstrating Mojo-V ISA rules and security semantics. The other Bringup-Bench benchmarks have not yet been ported to Mojo-V.

We welcome contributions, bug reports, and suggestions!

📧 Email: [email protected]
🌐 Project Home: https://github.com/toddmaustin/mojo-v