The Illinois Grainger Engineering team devised a process that achieves monolithic three-dimensional integration using standard single-crystal silicon. The method starts with creating ultrathin, freestanding silicon nanomembranes from a doner wafer, and these membranes are then transferred onto the receiving substrate that already contains completed bottom-layer circuits using a roll laminator. The process requires no more than 200 degrees Celsius to generate a strong bond between the substrate and the transferred layer. As a result, high performance and reliability were maintained with the high crystalline quality of the silicon films while the process stayed well within the thermal budget.
“Our method is not only easier to implement with lower cost, but it has several advantages over previous approaches to stack silicon wafers,” Cao said. “The membranes we transferred are only 10 nanometers thick or less, compared to the 500 to 700 micrometers thickness of a typical wafer. Because they are thin, these membranes are mechanically flexible to conform to the underlying surface. This conformality helps avoid interfacial defects like voids, which are common when trying to force two rigid wafers together via wafer bonding.”
The team also needed to rethink transistor design and fabrication. Conventional transistor fabrication requires a process known as “doping” to introduce impurities to the silicon to control its electrical properties. This is a high-temperature process typically exceeding 600 degrees Celsius, and different regions of the device need to be doped differently. To avoid this, the researchers used devices called “junctionless transistors” in which the silicon is uniformly and heavily doped before the layering step. Because the films are extremely thin, the gate can still control the channel effectively, while the high doping level reduces parasitic contact resistance.
Using this process, the team built three stacked layers, each containing 625 transistors, with good yield and uniformity. The output current densities of these transistors were comparable to that of standard silicon transistors fabricated on bulk wafers under a much higher temperature and at least three to four times greater than those of monolithic devices made from alternative materials, indicating a substantial improvement in performance. By connecting the layers with vertical metal lines, the researchers demonstrated three-dimensional integrated logic circuits and static random-access memory cells.
“But most importantly, we’ve shown that this process is scalable,” Cao said. “You can keep stacking layers beyond the three we demonstrated. And the process will yield high-performing transistors with high yield and low variability. We now have a strong foundation for transferring this technology and demonstrating its immediate promise in an industrial semiconductor foundry.”
Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shaloo Rakheja, and Jian-Min Zhuo also contributed to this study.
The article, “Monolithic three-dimensional integration of silicon transistors,” is available online. DOI: 10.1038/s41586-026-10496-6
Support was provided by the National Science Foundation, industry partners of the Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, and the Silicon Crossroads Microelectronics Commons Hub.
Illinois Grainger Engineering Affiliations
Qing Cao is an Illinois Grainger Engineering associate professor of materials science and engineering in the Department of Materials Science and Engineering. He is also affiliated with the Department of Electrical and Computer Engineeringand the Department of Chemistry. He is a member of the Materials Research Laboratory and the Holonyak Micro and Nanotechnology Laboratory.
Shaloo Rakheja is an Illinois Grainger Engineering associate professor of electrical and computer engineering in the Department of Electrical and Computer Engineering. She is the director of the Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). She is a member of the Holonyak Micro and Nanotechnology Lab and Coordinated Science Laboratory. She holds the Intel Alumni Endowed Faculty Fellow appointment.
Jian-Min Zhuo is an Illinois Grainger Engineering Professor Emeritus of materials science and engineering in the Department of Materials Science and Engineering.