Zettascale (YC S24) 正在招聘创始 FPGA 工程师
Zettascale (YC S24) Is Hiring Founding FPGA Engineers

原始链接: https://www.ycombinator.com/companies/zettascale/jobs/O9S1vqO-founding-engineer-fpga-rtl-asic-architect

Zetta 是一家雄心勃勃的初创公司,致力于通过开发用于驱动 AGI(通用人工智能)和 ASI(超级人工智能)的先进 XPU 芯片,成为下一个 NVIDIA。我们正在寻找一位硬核技术大牛加入我们在旧金山的创始团队,共同构建 AI 计算的未来。 **核心要求:** * **核心专长:** 对数字设计(VLSI、RTL、微架构)以及综合/时序收敛有深厚的专业知识。 * **技术能力:** 具备前端工具链(VCS/Genus)、脚本编写(Python、Tcl、Nix)及优化 PPA(功耗、性能、面积)的经验。 * **领域重点:** 在 GPU、CPU 或 AI 加速器的计算数据通路和内存子系统设计方面拥有成熟的背景。 * **思维方式:** 沉浸式、具备自学能力的博学之才,准备好在软硬件边界攻克近乎不可能的工程挑战。 **加分项:** 具有高速接口(PCIe、HBM)、可测试性设计(DFT)意识的 RTL、可复用 IP 设计以及系统级编程经验者优先。 **加入我们:** 您将在一家具有变革意义的公司中担任基石角色,并与顶尖工程师直接共事。我们提供具有竞争力的薪酬、可观的股权,以及参与“毕生之作”的机会,该项目旨在影响未来数代的技术发展。

抱歉。
相关文章

原文

At Zetta, we're building the next NVIDIA to accelerate AI discovery. Our XPU chips are state-of-the-art AI compute engines, versatile and efficient enough to support AGI, and eventually ASI, without requiring massive power infrastructure.

The team consists of exceptional engineers obsessed with pushing the boundaries of what's possible in computing, and we're now seeking our next technical member!

You Are

  • Ready to go all-in and do the work of your life
  • Willing to be hardcore when pushing technical boundaries
  • A technical powerhouse who loves working across the hardware-software boundary
  • Deeply passionate and obsessed with computing and AI
  • Hungry to build something that actually matters

Your Background (important in bold)

  • Background in Electrical Engineering, Computer Engineering, or equivalent field
  • Strong digital design fundamentals (VLSI, RTL, pipelining, clocking/reset strategy, latency/throughput tradeoffs, clean microarchitecture)
  • RTL quality discipline (lint, CDC/RDC, X-prop awareness, assertions/SVA, code review hygiene)
  • Synthesis/constraints expertise (SDC constraints, synthesis/PPA iteration, timing closure with physical design)
  • Proficiency with front-end toolchains (VCS/Xcelium/Questa, Verilator, SpyGlass-style linting, DC/Genus-class synthesis)
  • Build/flow automation and tooling (Python, Tcl, Nix)
  • Work across architecture, verification, and physical design to hit PPA targets (area/power/perf)
  • Experience designing compute datapaths and memory subsystems for AI accelerators, GPUs, or high-performance CPUs (bandwidth/latency-driven design)

Huge Plus If

  • High-speed interface/IP integration experience (PCIe, CXL, DDR/HBM, Ethernet, SerDes)
  • DFT-aware RTL (scan-friendly coding patterns, test hooks, clean resets, well-defined clock gating strategy)
  • Experience writing/maintaining reusable IP (parameterization, clean bus protocols, well-structured interfaces)
  • 1+ years (or equivalent) designing synthesizable RTL (SystemVerilog/Verilog) for ASICs and/or high-performance FPGA prototypes
  • HW/SW boundary experience (drivers/firmware bring-up, performance counters, profiling, build systems)
  • Experience with systems programming (Linux kernel modules, low-level)
  • Autodidactic polymath with a strong mathematical background
  • Someone who doesn't fret when faced with near-impossible technical challenges

The Opportunity

  • Be one of the first employees shaping a revolutionary technology
  • Work directly with the founding team of exceptional engineers at our San Francisco HQ
  • Own critical decisions that will influence the future of AI compute
  • Grow into a technical leader as we scale
  • Highly competitive compensation + significant equity

This is THE chance to do the work of your life. The chance to build something that will be remembered. To go hardcore on a technical moonshot that will actually matter for over 100 to 1,000 years.

联系我们 contact @ memedata.com