FPGA and embedded systems expert Adam Taylor has recreated the U.S. Navy’s F-14 Tomcat’s Central Air Data Computer (CADC) in an FPGA. The CADC is famous for being the brains behind the F14’s advanced fighter capabilities including the control of the aircraft’s signature articulated sweep-wing system. So, what better way to test the new FPGA than in a 3D printed scale model of the F-14 Tomcat? Check out the video embedded below.
We wrote about the F-14 Tomcat’s CADC last year after discussions erupted on social media about whether this flight computer was actually powered by the "world’s first microprocessor." The brains behind the CADC were provided by the MP944. This chip lived in the shadows for quite some time, though. Despite the MP944 microprocessor beginning service in June 1970, over a year before Intel’s legendary 4004 would become available (November 1971) it was an official secret until 1998. Thus, the Intel 4004 managed to steal the limelight from the true first microprocessor, say those in the MP944 camp.
To recap, the MP944 was a 20-bit, pipelined, parallel multi-microprocessor melded with state-of-the-art MOS technology and ran at 375 kHz, executing 9,375 instructions per second. The flight-system powering chip, designed by Steve Geller and Ray Holt and a 25-strong team, also passed stringent ruggedness tests and was capable of running in temperatures spanning -55 to +125 degrees Celsius.
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The MP944 worked as part of a six-chip system in the CADC, for the real-time calculation of flight parameters such as altitude, airspeed, and Mach number – and was a key innovation to enable the Tomcat’s articulated sweep-wing system. So it had to be performant, and some chip architecture enthusiasts assert that the MP944 was actually “8x faster than the Intel 4004.” Remember though, the Intel chip was originally designed for a far more humble desktop calculator.
Getting back to Adam Taylor’s recent achievement, and we now have a full open source set of VHDL source code, documentation, and testbenches for an FPGA recreation of the F‑14’s CADC. The GitHub repo says the FPGA used was a Spartan-7 based SoM, part of the Adiuvo Embedded System Tile. The resource isn’t just the MP944 logic, Taylor includes complete synthesizable VHDL implementations for all six original CADC chips.
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