ao486：实现 486 SX 所有功能的兼容 x86 的 Verilog 内核（2014 年）

ao486：实现 486 SX 所有功能的兼容 x86 的 Verilog 内核（2014 年）
ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)

**ao486** 是一个 x86 兼容的 Verilog 核心，实现了 486 SX 处理器，具有四级流水线、指令/数据缓存以及 TLB。该项目为 Terasic DE2-115（Cyclone IV E FPGA）开发，包含一个通过 Altera Qsys 建模的完整片上系统（SoC）环境。该 SoC 集成了必要的周边设备，包括 IDE/软盘控制器（重定向至 SD 卡）、8259 PIC、8237 DMA、Sound Blaster 2.0、VGA，以及用于系统管理和屏幕显示（OSD）的 NIOS II 处理器。该架构已成功测试运行 MS-DOS 6.22、Windows 95 和 Linux 3.13.1，并使用了来自 Bochs 和 VGABIOS 项目的修改版 BIOS 及 VGA BIOS 映像。综合需要使用 Altera Quartus II 软件，在 30 MHz 时钟速度下占用目标 FPGA 约 80% 的逻辑单元。该项目为开源项目，核心组件采用 BSD 和 LGPL 许可证，为 FPGA 硬件上的复古计算和 x86 硬件仿真提供了一个强大的平台。

这篇 Hacker News 的讨论围绕着 **ao486**（一款用于 MiSTer 平台的 x86 兼容 Verilog 核心）及其继任者 **z386** 展开。参与者指出，z386 目前的表现已超越 ao486，在《毁灭战士》（Doom）等游戏中的性能提升了约 30%。开发者将这一进展归功于近期对原始 80386 微代码的逆向工程与反汇编，这极大地提高了对复杂保护模式行为的仿真精度。讨论的很大一部分集中在 FPGA 实现的技术挑战上，特别是如何在 MiSTer 框架内管理多个像素时钟，以实现真实的模拟视频输出。该讨论帖还涉及了复古计算的法律层面；用户争论这些开源实现是否侵犯了知识产权，不过许多人指出，指令集架构（ISA）通常不受版权保护。总的来说，社区依然高度关注如何在周期精确（cycle-accurate）的性能表现与当前 FPGA 硬件的架构限制之间取得平衡。

原文

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX. The core was modeled and tested based on the Bochs software x86 implementation. Together with the 486 core, the ao486 project also contains a SoC capable of booting the Linux kernel version 3.13 and Microsoft Windows 95.

31 March 2014 - initial version 1.0.
19 August 2014 - driver_sd update, ps2 fix.

The ao486 processor model has the following features:

pipeline architecture with 4 main stages: decode, read, execute and write,
all 486 instructions are implemented, together with CPUID,
16 kB instruction cache,
16 kB write-back data cache,
TLB for 32 entries,
Altera Avalon interfaces for memory and io access.

The ao486 SoC consists of the following components:

ao486 processor,
IDE hard drive that redirects to a HDL SD card driver,
floppy controller that also redirects to the SD card driver,
8259 PIC,
8237 DMA,
Sound Blaster 2.0 with DSP and OPL2 (FM synthesis not fully working). Sound output redirected to a WM8731 audio codec,
8254 PIT,
8042 keyboard and mouse controller,
RTC
standard VGA.

All components are modeled as Altera Qsys components. Altera Qsys connects all parts together, and supplies the SDRAM controller.

The ao486 project is currently only running on the Terasic DE2-115 board.

The project is synthesised for the Altera Cyclone IV E EP4CE115F29C7 device. Resource utilization is as follows:

Unit	Logic cells	M9K memory blocks
ao486 processor	36517	47
floppy	1514	2
hdd	2071	17
nios2	1056	3
onchip for nios2	0	32
pc_dma	848	0
pic	388	0
pit	667	0
ps2	742	2
rtc	783	1
sound	37131	29
vga	2534	260

The fitter raport after compiling all components of the ao486 project is as follows:

Fitter Status : Successful - Sun Mar 30 21:00:13 2014
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : soc
Top-level Entity Name : soc
Family : Cyclone IV E
Device : EP4CE115F29C7
Timing Models : Final
Total logic elements : 91,256 / 114,480 ( 80 % )
    Total combinational functions : 86,811 / 114,480 ( 76 % )
    Dedicated logic registers : 26,746 / 114,480 ( 23 % )
Total registers : 26865
Total pins : 108 / 529 ( 20 % )
Total virtual pins : 0
Total memory bits : 2,993,408 / 3,981,312 ( 75 % )
Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % )
Total PLLs : 1 / 4 ( 25 % )

The maximum frequency is 39 MHz. The project uses a 30 MHz clock.

The package DosTests.zip from http://www.roylongbottom.org.uk/dhrystone%20results.htm was used to benchmark the ao486.

Test	Result
Dhryston 1 Benchmark Non-Optimised	1.00 VAX MIPS
Dhryston 1 Benchmark Optimised	4.58 VAX MIPS
Dhryston 2 Benchmark Non-Optimised	1.01 VAX MIPS
Dhryston 2 Benchmark Optimised	3.84 VAX MIPS

The ao486 successfuly runs the following software:

Microsoft MS-DOS version 6.22,
Microsoft Windows for Workgroups 3.11,
Microsoft Windows 95,
Linux 3.13.1.

The ao486 project uses the BIOS from the Bochs project (http://bochs.sourceforge.net, version 2.6.2). Some minor changes were required to support the hard drive.

The VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios, version 0.7a). No changes were required. The VGA model does not have VBE extensions, so the extensions were disabled.

The ao486 SoC uses a Altera NIOS2 processor for managing all components and displaying the contents of the On Screen Display.

The OSD allows the user to insert and remove floppy disks.

All files in the following directories:

are licensed under the BSD license:

All files in the following directories:

are taken from the Bochs Project and are licensed under the LGPL license.

The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.

The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.

The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios project.

To compile the SoC, which contains the NIOS II microcontroller, Altera Quartus II software is required. The Verilog components of the SoC, in particular the ao486 processor, should be possible to compile in any Verilog compiler. Currently synthesis project files are prepared only for Altera Quartus II.

NOTE: In the current version some synthesis project files -- especially the paths in those files, could be broken.

To compile the ao486 processor load the project file from syn/components/ao486/ao486.qpf.

To compile the ao486 SoC load the project file from syn/soc/soc.qpf.

Before compiling in Altera Quartus II, the Qsys system must be generated.

To compile the BIOS do the following:

extract the bochs-2.6.2 source archive,
apply the patch from the directory bios/bochs-2.6.2 by running in the extracted directory: patch -p1 < (path to patch file)
run ./configure in bochs
run make in bochs
cd bios
make
the binary file BIOS-bochs-legacy works with ao486 SoC.

To compile the VGABIOS do the following:

extract the vgabios-0.7a source archive,
apply the patch form the directory bios/vgabios-0.7a by running in the extracted directory: patch -p1 < (path to patch file)
run make in vgabios,
the binary file VGABIOS-lgpl-latest.bin works with ao486 SoC.

Running the SoC on Terasic DE2-115

compile the soc Altera Quartus II project in syn/soc/soc.qpf
compile the firmware for the NIOS II by:
- opening the Nios II Software Build Tools for Eclipse,
- creating a workspace in the directory syn/soc/firmware,
- importing the two projects 'exe' and 'exe_bsp',
- genrating BSP on the 'exe_bsp' project,
- compiling the 'exe' project.
compile the BIOS and copy the binary to the directory sd/bios,
compile the VGABIOS and copy the binary to the directory sd/vgabios,
compile the ao486_tool by running 'ant jar' in the directory ao486_tool,
edit the files in the directory sd/hdd. They contain the position of the virtual hard disk located on the SD card. The start entry must be a multiplicity of 512. The values are in bytes from the begining of the SD card,
run 'java -cp ./dist/ao486_tool.jar ao486.SDGenerator' in the directory ao486_tool,
copy the file ao486_tool/sd.dat to the first sectors of the SD card by using 'dd if=sd.dat of=/dev/sdXXX'.
insert the SD card to the Terasic DE2-115 board,
program the FPGA using the SOF file,
load and run the firmware of the NIOS II controller,
select the BIOS file on the On Screen Display by using KEY0 for down, KEY1 for up and KEY2 for select,
select the VGABIOS file on the OSD,
select the hard drive on the OSD,
select the floppy on the OSD. Use the KEYs to select the floppy image. Use KEY3 to cancel.
after selecting the floppy or pressing cancel, ao486 boots,
to activate the OSD press KEY2.

ao486：实现 486 SX 所有功能的兼容 x86 的 Verilog 内核（2014 年） ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)

Running the SoC on Terasic DE2-115

ao486：实现 486 SX 所有功能的兼容 x86 的 Verilog 内核（2014 年）
ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)