AMD 矩阵核心的精确模型
Accurate Models of AMD Matrix Cores

原始链接: https://arxiv.org/abs/2609.14845

本文探讨了现代 GPU 矩阵乘法器中缺乏 IEEE 754 标准合规性的问题,并指出舍入方式、累加器宽度和非规格化数处理等未公开的实现细节,导致了不同硬件间数值结果无法复现。 研究人员对三种 AMD GPU 架构(CDNA 1、CDNA 2 和 CDNA 3)的矩阵核心数值行为进行了表征。通过设计特定的测试向量并采用迭代式的随机细化过程,研究人员为每种架构开发了高保真的 MATLAB 软件模型。这些模型通过 1000 万组随机输入数据进行了验证,确保了与硬件层面的位级精度一致。 该研究最终利用这些模型对比了 AMD 矩阵核心与 NVIDIA 张量核心的精度,展示了这些模型在实验研究和跨厂商数值分析中的应用价值。

近期 Hacker News 上的一场讨论强调了各 AI 加速器中非标准化、无文档的矩阵乘法实现所带来的挑战。由于厂商采用不同的硬件架构、分块策略及舍入行为,目前在不同设备间实现矩阵运算的可复现结果是不可能的。 虽然一些评论者认为这些差异会导致软件崩溃,但另一些人则认为,崩溃更可能是由驱动程序错误、内存对齐问题或不兼容的指令集引起的,而非单纯源于数值精度。 这场辩论触及了一个更广泛的技术难题:缺乏类似于 IEEE-754 的通用矩阵乘法标准。一些人提出,这样的规范对于行业稳定性是必要的。然而,批评者指出,浮点运算在不同硬件间从未实现过完美的一致性,强制执行严格的标准可能会抑制创新和算法优化,而这些优化正是现代加速器实现高性能的关键。归根结底,开发人员目前被迫应对一个碎片化的生态系统,在不同 GPU 架构间迁移代码时,往往需要进行大量底层调整。
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原文

View a PDF of the paper titled Accurate Models of AMD Matrix Cores, by Faizan A Khattak and Mantas Mikaitis and Carlo J. Graziani

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Abstract:Matrix multipliers available on recent GPUs do not conform with the IEEE 754 floating point standard. Features of matrix multipliers differ across vendors and architectures of the same vendor, such as accumulator width, rounding behaviour, normalisation points, intermediate underflow and overflow logic, the handling of subnormals, and the treatment of special inputs. As a result, reproducibility of small matrix multiplier results across devices is not possible and cannot be achieved by software control. Implementation details of matrix multipliers are not documented, making it difficult to interpret discrepancies in the computed results. We characterise the numerical behaviour of matrix multipliers across three AMD GPU architectures: CDNA 1, CDNA 2, and CDNA 3, using the MI100, MI210/250, and MI300A/300X GPUs, respectively. We design test vectors to target numerical features for all supported input formats and provide the derivation and the reasoning for why each vector allows to determine a particular numerical feature based on the outputs of the devices. MATLAB-based software models of the matrix multipliers are then developed for each architecture and validated for bit-level reproducibility against hardware using a randomized test suite consisting of 10 million sets of random input vectors. To achieve this, we applied a previously developed technique to iteratively refine the accuracy of the models in a loop, by randomized testing followed by test-refinement until the model matches the hardware for every test case. Finally, as a proof of concept for what experimental research can be done with the models, we have utilised them in two demonstrative numerical applications, quantifying application-level accuracy differences between AMD matrix cores and the NVIDIA tensor cores.
From: Faizan Ahmad Khattak [view email]
[v1] Sun, 13 Sep 2026 23:34:01 UTC (1,297 KB)
[v2] Tue, 15 Sep 2026 10:33:08 UTC (1,297 KB)
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