;-------------------------------------------------------------------------------+ ; + ; Documentation: + ; + ; There are several methods for identifying CPUs. For this documentation, I + ; will concentrate on how to detect different 32-bit processors (as that + ; is all that I am targetting for my OS). I will have more information on + ; detecting other processors on a web site soon. + ; + ; For the purpose of this code, we only need to check if we have a 386 or later + ; processor, and then we can test which processor is present. + ; + ; Debbie Wiles + ; [email protected] + ; + ; + ;-------------------------------------------------------------------------------+ ; Early processor identification: + ; + ; CPU Method + ; + ; 808x/186+ Shift register by 32. Clears register on 808x and NEC V2/30. + ; This is because later CPUs mask sift/rotate value with 01Fh. + ; 808x/NEC PUSHA; NOP; + ; pusha is executed on V20/30, so we can check if SP has changed. + ; On 808x, pusha executes as a 2-byte nop, so SP is not changed. + ; 808x/80C8x REP ES: MOVSB ; CX = 0FFFFh + ; Test within a loop. If CX is non-zero at the end of a loop, + ; then it is a NMOS chip. If always zero, it is CMOS. + ; 18x/286 PUSH SP + ; On 286 and later, the original value of SP is stored. + ; On 18x and earlier, the new value is stored. + ; 8/16-bit Use self-modifying code (808x/8018x/Vx0) + ; The prefetch queue on 8-bit processors is 4 bytes long. + ; The prefetch queue on 16-bit processors is 6 bytes long. + ; For example, change a NOP to an INC. If executed as INC, we + ; we have an 8-bit processor. + ; ---------------------------------------------------------------- + ; ---------------------------------------------------------------- + ; 286/386+ Test behaviour of flags[12-15]. + ; 808x and 8018x: flags[12-15] are always set. + ; 286: flags[12-15] are always clear in real-address mode. + ; 32-bit processors: real-mode: + ; bit 15 is always clear; + ; bits 12-14 have the last value loaded into them. + ; 32-bit processors: protected mode: + ; bit 15 is always clear; + ; bit 14 has the last value loaded into it; + ; and the IOPL bits depends on the (CPL). + ; The IOPL field can be changed only if the CPL is 0. + ; ---------------------------------------------------------------- + ; ---------------------------------------------------------------- + ; 486 Flags[18] can be changed on 486 and later processors. + ; ---------------------------------------------------------------- + ; ---------------------------------------------------------------- + ; 386DX To determine the stepping of 386DX: + ; Stepping B0 and earlier support IBTS/XBTS, later don't. + ; Stepping B1, rep insb with CX=1 doesn't clear CX + ; + ; NexGen Nx586 + ; When we know it's a 386 (and not a 486), we can do a div test: + ; + ; xor ax,ax ; clear ax + ; sahf ; clear flags, + ; ; bit 1 of flags is always set + ; + ; mov ax,5 ; move 5 into the dividend + ; xor dx,dx + ; mov bx,2 ; move 2 into the divisor + ; div bl ; perform div test + ; + ; jz is_NexGen ; flags not changed, + ; ; it's a NexGen CPU + ; + ; ZF will never be set on a NexGen CPU, but will be set on others.+ ; + ; 386SX/DX (Also Cx486SLC/DLC) +Done ; If CR0 bit 4 can be cleared, we have a 386, 386DX or Cx486DLC. + ; If it cannot be cleared, it is a 386SX, 486SLC or a 'real' 486. + ; Always restore CR0 (MSW) after this test. + ; + ; i386 EX has 64M memory space + ; SX has 16M memory space + ; DX has 4G memory space + ; + ; Am386SX/SXL/SXLV + ; If you can execute SMM instructions, it's an SXLV. + ; + ; C&T 386's +Done ; This involves a test for the 386 POPAD bug. + ; The 386 POPAD bug affects all 386DX and early 386SX revisions. + ; I don't have any complete documentation for this, only what + ; RBIL says. + ; Psuedo-code: + ; Set EAX=12345678h ; value that won't roate to same value. + ; set i = 32 + ; DO{ + ; set EBX = EAX + ; clear EDX and EDI + ; push all and pop all (32-bit) + ; set ECX = [EDX + EDI] + ; IF(EAX EBX) exit loop. + ; rotate EAX left by 1 + ; decrement i + ; } WHILE(i > 0) + ; + ; If i = 0, we have a C&T 386, otherwise it's an AMD or Intel. + ; ---------------------------------------------------------------- + ; ---------------------------------------------------------------- + ; CPUID Flags[21] can be changed on processors which support CPUID. + ; ---------------------------------------------------------------- + ; ---------------------------------------------------------------- + ; Cyrix Finds Cyrix, TI, SGS, IBM processors. + ; First check that it is a 486+, then: + ; Method 1: + ; For pre-Pentium and non-SMI modes: + ; UMOV executed as double NOP on Cyrix processors. + ; Method 2: + ; Divide test: + ; Store 0 to flags low byte (bit 1 always set). + ; Divide 5 (in AX) by 2 (Cyrix show it in BL). + ; Read low byte of flags (LAHF). + ; If not equal to 2, it's not a Cyrix processor. + ; + ; IBM 386/486 SLC, 486BL3 (others??) + ; Test initially as 486 and Cyrix. + ; IBM 386 and some 486 use MSRs. + ; + ; UMC I'm not sure what this does. I got it from RBIL. + ; Use this for UMC U486SX. For other UMC processors, use CPUID. + ; + ; db 64h,0dbh ; looks like "SALC FS:", but it's not. + ; cmp eax,0ab6b1b07h + ; je u486SX + ; jne Other + ; + ; FPU (Checks for any processor with FPU) + ; Test for FPU: + ; Clear a memory area [mem] + ; Initialise FPU (perform FNINIT) + ; Store FPU control word to [mem] (perform FNSTCW [mem]) + ; If [mem] is 037Fh, then we have an FPU present. + ; + ; SMM Use UMOV to test for SMM enabled and SL enhanced AMD 386/486s, + ; and IBM 486SLC2. + ; If no SMM, it will generate a #UD. + ; Cyrix executed this as a double nop. + ; Only use this test on 386/486, and make sure it's not a UMC + ; processor first, as they will hang. + ; + ;-------------------------------------------------------------------------------+ ; + ; Visually identifying processors: + ; + ; AMD + ; + ; 486 E6 9425APH + ; 5x86 * * * + ; * * **** ??? + ; * ******** Year/Week of manufacture + ; *********** Revision + ; + ; K5 C 9718GPA + ; * * * + ; * * **** ??? + ; * ******** Year/Week of manufacture + ; *********** Revision: A/B/../G + ; + ; K6 A 9845CPAW + ; K6-2 * * * + ; K6-3 * * **** ??? (EPAW on K66-III ??) + ; * ******** Year/Week of manufacture + ; *********** Revision: A/B/../G + ; + ; Cyrix + ; + ; 6x86 XXYYZ734C + ; 6x86L * * ** * + ; * * ** *** Lot Number + ; * * ******* Year/Week (7 = 1997) + ; * * ******* Mask Revision + ; * ********* ?? (DC/DD/DE/DJ are known...) + ; *********** Version + ; + ; Version Mask Stepping + ; Number Revision + ; + ; G8 ? 2.x + ; 3 2.4 + ; 4 2.5 + ; 5 2.6 + ; 6 2.7 + ; G9 ? 3.x + ; A 3.7 + ; B 3.8 + ; + ; GA ? 4.x 6x86L + ; 3 + ; + ; GE ? ??? + ; + ; Intel + ; + ; i386EX Lot code ends in: Stepping: + ; + ; A/B A + ; C A (Manuals) + ; C B (Website) + ; D B + ; E C + ; 1/2 B (Special Environment) + ; + ; i486DX4 S-Spec Info + ; + ; SK050 Supports CLK x2 and CLK x3 + ; SK053 Ditto + ; SK099 Ditto + ; SX876 Ditto + ; SX877 Ditto + ; + ; others Not tested at CLK x 2 + ; + ; + ;-------------------------------------------------------------------------------+ ; + ; Identifying Cyrix/TI/IBM/ST CPUs + ; + ; Once we know it is a Cyrix (or clone): + ; + ; See if we can toggle CCR2 bit 3 (Lock_NW) and CCR3 bit 4 (MAPEN). + ; The results tell us the following: + ; + ; Can the bit be toggled? + ; + ; CCR2.2 CCR3.4 Processor(s) + ; + ; No No Cyrix/TI 486SLC/DLC, no DIRs + ; TI 486SXLC/SXL, no DIRs + ; IBM SLC/SLC2, no DIRs + ; Yes No Cyrix 486S A-step processor w/out DIRs + ; No Yes Cx486SLC/DLC with DIRs + ; Yes Yes Other Cyrix with DIRs + ; + ; If the processor has DIRs, we can use them to determine the CPU type. + ; + ; If it has no DIRs and is not a 486S: + ; + ; Test for SLC/DLC etc + ; + ; If CR0.4 can be cleared, it's a DLC or SXL + ; IBM has MSRs. Test MSR 1000h (non-IBM gives exception 13). + ; See next section for IBM details. + ; + ; Test cache size using TR4 and 5. + ; + ; Disable cache (TR7.11 = 1 ??) + ; Write 200h to TR4 (on Cx486SLC: is cache line entry valid?). + ; Write 1 to TR5 (cache line write) + ; Write 2 to TR5 (cache line read) + ; Read TR4. If bit 9 is set, it has 1k cache, else it has 8k. + ; + ; +------------------------------+ + ; 16-bit bus32-bit bus + ; +--------+----------+---------- + ; 1k cacheCx486SLC Cx486DLC + ; 8k cacheTI486SXLC TI486SXL + ; +------------------------------+ + ; + ; For SLC/DLC etc: + ; + ; Stepping A has no SMM, Stepping B has them. + ; + ; Enable SMM instructions and then check if legal. + ; (does this involve a specific SMM instruction, such as UMOV?) + ; + ; For 5x86 and 6x86, we need to set ccr4.7 in order to use CPUID. + ; + ; Cyrix Processors ID using DIR registers. + ; + ; Write to port 22h with the index, read from 23h. + ; + ; DIR0 Index 0FEh + ; DIR1 Index 0FFh + ; + ; DIR values: + ; + ; Bits Description + ; + ; DIR0[7-4] CPU Device ID Number + ; DIR0[3-0] CPU Clock Multiplier + ; + ; DIR1[7-4] CPU Step ID Number + ; For TI486DX2, stepping eB0 and later, bit 7 is set. + ; DIR1[3-0] CPU Revision ID + ; + ; Specific DIR values are listed in the bottom table on this page. + ; + ;-------------------------------------------------------------------------------+ ; + ; IBM MSRs (Taken from MSR.LST, distributed with RBIL) + ; + ; MSR 00001000h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER + ; + ; Size: 19 bits + ; Access: Read/Write + ; + ; Bitfields for IBM 386/486 SLC Processor Operation Register: + ; + ; Bit(s) Description + ; 63-19 reserved + ; 18 (486SLC only) Low Power PLA + ; 17 (486SLC only) Bus Read + ; 16 (486SLC only) Cache Parity Generate Error + ; 15 enable cacheability of NPX operands + ; 14 enable PWI ADS + ; 13 enable Low Power Halt Mode (HLT instruction stops CPU clock) + ; 12 extended Out instruction (CPU waits for READY after any output) + ; 11 cache reload bit + ; 10 enable internal KEN# signal + ; 9 disable cache lock mode + ; 8 reserved + ; 7 enable cache + ; 6 enable DBCS + ; 5 enable Power Interrupt + ; 4 enable Flush Snooping + ; 3 enable Snoop Input + ; 2 address line A20 mask + ; 1 enable cache parity checking + ; 0 Cache Parity Error occurred + ; + ; + ; MSR 00001001h - IBM 386/486 SLC - CACHE REGION CONTROL REGISTER + ; + ; Size: 48 bits + ; + ; Bitfields for IBM 386/486 SLC Cache Region Control Register: + ; + ; Bit(s) Description + ; 63-48 reserved + ; 47-32 extended memory cache memory limit (number of 64K blocks above + ; 1M which may be cached) + ; 31-16 first megabyte read-only flags (each bit represents 64K) + ; 15-0 first megabyte cacheable flags (each bit represents 64K) + ; + ; + ; MSR 00001002h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER + ; + ; Size: 30 bits + ; + ; Bitfields for IBM 386/486 SLC Processor Operation Register: + ; + ; Bit(s) Description + ; 63-30 reserved + ; 29 enable External Dynamic Frequency Shift + ; 28 Dynamic Frequency Shift ready + ; 27 Dynamic Frequency Shift Mode + ; 26-24 clocking mode + ; 000 clock x1 + ; 011 clock doubler + ; 100 clock tripler + ; 23-0 reserved + ; + ; + ; MSR 00001004h - IBM 486BL3 - PROCESSOR CONTROL REGISTER + ; + ; Size: 24 bits + ; + ; Bitfields for IBM 486BL3 Processor Control Register: + ; + ; Bit(s) Description + ; 63-24 reserved + ; 23 OS/2 boot (0=DD1 hardware, 1=DD0 hardware) + ; 22 MOV CR0,x Decode + ; 0: DD0, DD1A, DD1B, DD1D hardware + ; 1: DD1C hardware + ; 21 reserved + ; 20 Cache Low Power (DD1 only: cache disabled when not in use) + ; 19 reserved + ; 18 NOP timing + ; 0: 2 cycles on DD0, 3 cycles on DD1 + ; 1: 3 cycles on DD0, 2 cycles on DD1 + ; 17 bus pipelining for 16-bit accesses + ; 16-5 reserved??? + ; 4 MOVS split + ; 3 power-saving cache feature + ; 2 reserved + ; 1 enable MOV CRx decode + ; (reserved on DD1B, DD1C) + ; 0 reserved + ; + ;-------------------------------------------------------------------------------+ ; + ; EDX Reset signatures + ; + ; This can take two different forms, one for 386 and alike, the other for 486 + ; and higher, while some Cyrix CPUs have a reset value which is formed + ; from the values in DIR0 and DIR1 (this can be ignored, as we will read + ; the DIRs for those Cyrix chips). The information I have seen about + ; this is different in RBIL to that in Grzegorz Mazurs pages. So far, + ; I have been unable to test this, so I will include what data I have, + ; but my ID code will use the DIRs for Cyrix chips. This will provide + ; an additional method of differentiating between some Cyrix processors + ; and their clones, while also enabling them to be differentiated from + ; Intel and AMD processors. + ; + ; The CPU ID number can sometimes be returned by the BIOS. Use: + ; + ; Int 15h, AX = 0C910h (PS2 & some others) + ; + ; Int 15h, AX = 0DA92h (AMI PCI BIOS) (also returns speed) + ; + ; Additionally, some odlder BIOSes have a function to return the CPU speed + ; + ; Int 15h, AX = 2305 (IBM BIOS - Smart Energy System)(Up to 80MHz) + ; + ;-------------------------------------------------------------------------------+ ; + ; CPUID Return values: + ; + ; CPUID with EAX=0 Returns a vendor ID string in EDX:ECX:EAX + ; + ; String Vendor + ; + ; "GenuineIntel" Intel Corp. + ; "AuthenticAMD" Advanced Micro Devices. + ; "AMD ISBETTER" Some AMD Samples? (1994, according to Grzegorz Mazur) + ; "CyrixInstead" Cyrix Corp., now part of VIA + ; "UMC UMC UMC " United Microelectronics Corporation. + ; "NexGenDriven" NexGen Inc. + ; "CentaurHauls" IDT/Centaur, VIA + ; "RiseRiseRise" Rise + ; "GenuineTMx86" Transmeta + ; + ; Note that IDT processors can have a false ID string written in to them. + ; To correctly identify them: + ; + ; execute CPUID with EAX = 0xC0000000 + ; if EAX 0xC0000000, it's not an IDT + ; execute CPUID again with EAX = 0, and Vendor string will be correct. + ; If it now says IDT, then the only way to guarantee a correct processor + ; value is to reset the CPU. + ; + ; CPUID Return values in EAX for input value of 1. + ; + ; AX = TYPE:FAMILY:MODEL:STEPPING + ; + ; Type Meaning + ; + ; 0 Standard CPU + ; 1 Overdrive + ; 2 2nd CPU in dual-processor system, or overdrive set as 2nd CPU. + ; + ; 386: EDX[15-12] = Model + ; EDX[11-08] = Family + ; EDX[07-00] = Mask + ; + ; 486+: EDX[15-12] = Type + ; EDX[11-08] = Family + ; EDX[07-04] = Model + ; EDX[03-00] = Mask + ; + ;-------------------------------------------------------------------------------+ ; + ; Processor IDs. + ; + ; These IDs are those returned in the low word of EDX at reset, and EAX + ; after executing CPUID with EAX=1. + ; + ; Source: + ; R: RBIL + ; M: Manual + ; G: Grzegorz Mazur + ; P: Plasma Online (http://www.plasma-online.de/index.html) + ; S: Sandpile + ; L: Chiplist + ; B: 86Bugs list + ; X: Linux sources + ; C: Confirmed by myself. + ; + ; 386 processor signatures (most need a CPU reset): + ; + ; M = Model + ; F = Family + ; SS = Stepping + ; + ; MFSS Processor Stepping Comments +Source ; + ; 00xx i386DX A 12 MHz +RPL ; + ; 0300 i386DX A +GMS ; 0300 C&T 38600DX/SX 33-40 MHz, CPUID +P ; 0300 C&T 38605DX/SX 33-40 MHz, CPUID +P ; 512 byte instruction cache + ; + ; 0303 i386DX B0-B10 16-33 MHz +RGPMLS ; + ; 0304 i386DX ? 16-33 MHz +RPmB ; + ; 0305 i386DX D0 16-33 MHz +RGPMLSBC ; 0305 Am386DX(L/LV) A +RGSL ; + ; 0308 i386DX D1,D2,Ex,Fx 16-33 MHz +RGPMLSBC ; 0308 Am386DX(L/LV) B +RGSL ; + ; 030x i386DX any +GMls ; 030x Am386DX any 16-40 MHz, P says xx = 5-8 +RGMP ; 030x Am386DXL any 20-40 MHz +RGMP ; 030x Am386DXLV any 20-33 MHz, SMM +RGMP ; + ; 0340 RapidCAD (tm) A 486DX O/D, 25-33 MHz +RGPLS ; + ; 0341 RapidCAD (tm) B 486DX O/D, 25-33 MHz +RGPLS ; + ; 034x RapidCAD (tm) any 486DX O/D, 25-33 MHz +rgMpls ; L: consists of two chips + ; + ; 2304 i386SX A0 16-33 MHz +RPMgLSB ; + ; 2305 i386SX B 16-33 MHz +RPMgLSB ; 2305 Am386SX(L/LV) A1 +RgSL ; + ; 2306 i386SX C ??? 16-33 MHz +BS ?? ; + ; 2308 i386SX C-E 16-33 MHz +BRPMgLSC ; 2308 Am386SX(L/LV) B +RgSL ; + ; 2309 i386SX D ? 16-33 MHz +S?l? ; 2309 i386CXSA A +RMgLS ; 2309 i386CXSB A +RgSL ; 2309 i386EX A0,B1,C1 +RMgSL ; + ; 2309 i386SXSA A Embedded SX, 16-25 MHz +RPMgS ; + ; 230x Am386SX any 16-40 MHz, P says xx = 5-8 +rgMPL ; 230x Am386SXL any 20-40 MHz +rgMPL ; 230x Am386SXLV any 20-33 MHz, SMM +rgMPL ; 230x i386SX any 16-33 MHz +GMls ; 230x i386CX any SX, 12-25 MHz, Static core, SMM +gMsl ; 230x i386EX any SX, 16-25MHz, Static core, SMM +gMsL ; + ; 3305 i376 A0 +RMgSL ; + ; 3308 i376 B +RMgSL ; + ; 33xxh i376 any Embedded SX, 16-20MHz, +rGPMls ; Pmode only + ; + ; 4303 i386SL ? From C`T, 9/92, p156 + ; + ; 4305 i386SL A0-A3 ? +Rg ; + ; 4310 i386SL A0-A3 Reset ID +SLP ; + ; 4311 i386SL B0-B1 Reset ID +SLP ; + ; 431x i386SL B0-B1 +PRlg ; + ; 43xx i386SL any P says mask = 10-11. +PrGlM ; w/chipset 82360SL, 16-33 MHz + ; L,R says: signature register + ; (OMCU) at 0x30E + ; Value Step + ; 4300 A0,A1 + ; 4301 A2 + ; 4302 A3 + ; 4310 B0 + ; 4311 B1 + ; + ; A301 IBM 386SLC ? +G ; + ; A3xx IBM 386SLC A 8K cache to be enabled by s/w +RgpL ; A3xx IBM 386SLC any +rGP ; + ; 486 processor signatures (many need a CPU reset): + ; + ; ID = TFMS + ; + ; T = Type + ; F = Family + ; M = Model + ; S = Stepping Mask + ; + ; ID Processor Stepping Comments + ; + ; 0000 486DX A1 +B ; + ; 0005 Cx486S any SMM +RL ; 0005 Cx486D any +RL ; + ; 0006 Cx486DX any +RL ; + ; 0007 Cx486DX2 any +RL ; + ; 0008 Cx486DX4 any +R ; + ; 0400 i486DX A0,A1 25-33 MHz +RPmSgL ; + ; 0401 i486DX B2-B6 25-33 MHz +RPmSgLB ; Am486DX B3-B6 +M ; + ; 0402 i486DX C0 25-33 MHz +RPmSgLB ; 0402 Am486DX C0 +M ; + ; 0403 i486DX C1 25-33 MHz +RPmSgL ; + ; 0404 i486DX D0 25-33 MHz +RPmSgLBC ; 0404 Am486DX D0 +M ; + ; 0405 Some i486DX CPUID +Gms ; + ; 040x i486DX "P4" P indicates mask 0-4 only. +GPMSX ; M says no CPUID + ; + ; + ; 0410 i486DX50 cA2,cA3 +RPmSgLB ; 0410 Am486DX cA2,cA3 +Mg ; 0410 Cx486SLC A +Rl ; 0410 TI486SLC/DLC/e A +RPL ; 0410 TI486SXL(C)/2 A +RPL ; + ; 0411 i486DX50 cB0,cB1 +RPmSgLB ; 0411 Am486DX cB0 +Mg ; 0411 TI486SLC/DLC/e B +RPL ; 0411 TI486SXL(C)/2 B +RPL ; + ; 0412 Am486DX any contradicted by manuals +RgSL ; S says up to 40MHz + ; 0412 Am486DXL any 40MHz +PgL ; 0412 Am486DXLV any 33MHz, SMM +PgL ; 0412 Am486DE ? any ??? +Pg ; + ; 0413 i486DX50 cC0 +RPmSgLC ; + ; 0414 i486DX50 aA0,aA1 SL Enahnced +RPmSgl ; + ; 0415 i486DX50 aB0 SL Enahnced +RPmSGLC ; + ; 041x i486DX50 "P4S" ? P says 0-5, R says no 2. +GPMsX ; M says no CPUID + ; 041x Am486DX any +GPML ; 041x UMC U5SD (486DX), CPUID +GSL ; DX pin compatible U5S + ; 041x UMC U5D +X ; 041x Cx486SLC +rL ; 0411 TI486SXL(C)/2 SXL/SXLC/SXL2/SXLC2 +RPL ; also, -v = low power + ; + ; 0420 i486SX A0 +RPSgLB ; 0420 i487SX A0 Full DX, disables SX +RP ; 0420 Cx486SLC A +M ; + ; 0422 i486SX B0 +RPSgLC ; 0422 i487SX B0 Full DX, disables SX +RP ; + ; 0423 i486SX bBx SL Enahnced +RPsgC ; 0423 i486SX D +SL ; 0423 UMC U5S A,any 486SX, CPUID +RGsL ; + ; 0424 i486SX gAx +RPSgL ; + ; 0427 i486SX cA0 CPUID +RGPSL ; + ; 0428 i486SX cB0 CPUID +RGPSLC ; 0428 Cx5x86 (x1) 1+ CPUID result +M ; + ; 0429 Cx5x86 (x2) 1+ CPUID result +RM ; + ; 042A i486SX aA0,aA1 SL Enahnced +RPSgLC ; 042A i486SX E Check this one... +SL ; 042A Cx5x86 (x1) 1+ CPUID result +M ; + ; 042B i486SX aB0,aC0 SL Enahnced +RPsgL ; 042B Cx5x86 (x2) 1+ CPUID result +RM ; + ; 042C Cx5x86 (x4) 1+ CPUID result +M ; + ; 042D Cx5x86 (x3) 1+ CPUID result +RM ; + ; 042E i486SX E +GS ; 042E i486SX E CPUID +Gs ; 042E Cx5x86 (x4) 1+ CPUID result +M ; + ; 042F Cx5x86 (x3) 1+ CPUID result +RM ; + ; 042x i486SX "P23" ? P says 0-B, 16-33 MHz, 8K L1 +GPMSLX ; 042x i486SX "P23S" ? SL Enahnced +GPL ; 042x i486GX ? Embedded, Ultra Low Power +M ; 042x i487SX "P23N" P implies 0-B ? +P ; 042x Cx486SLC +Lm ; 042x Cx5x86 1+ CPUID result +R ; 042x UMC U5S +X ; + ; 0432 i486DX2 A0-A2 +RPmSL ; 1432 i486DX2 A0-A2 overdrive +RPms ; 0432 Am486DX2 any 66 & 80 MHz, CPUID? +RGMsC ; 0432 Am486DXL2 any +RPL ; 0432 Am486DX4 any NV8T, WT mode only +RGMSL ; + ; 0433 i486DX2 B1 +RPmSLC ; 1433 i486DX2 B1 Overdrive +rpmsLC ; + ; 0434 i486DX2 aA0,aA1 SL Enahnced +RGPmSL ; 1434 i486DX2 aA0,aA1 SL Enahnced, overdrive +RGPmsL ; 0434 Am486DX2-66 x2 ? WT mode, CPUID +GMPs ; 0434 Am486DX4 x2 ? SV8B, WT mode, CPUID +GMS ; + ; 0435 i486DX2 aB0,aC0 SL Enahnced, (O/D?) +RGPmSLC ; + ; 0436 i486DX2WT any 436 on CPUID if WT (see 470) +RGPmS ; stepping needs a reset +S ; A + ; + ; 043x UMC U486DX2 any CPUID +RL ; 043x i486DX2 "P24" any 8K L1, 40-66 MHz, step 2-5 +RPMsLX ; 043x i486DX2 "P24S" any SL enhanced +RPMsL ; 143x i486DX2 "P23T" any Overdrive for 486SX +RPmsL ; 143x i486DX2 "P24T" any Overdrive +RPmsL ; 043x i487SX "P23N" +M ; 043x Am486DX2 any Standard version, 50-100 MHz +MSLx ; 043x Am486DX2 any SV8B, WT, CPUID, 66-100 MHz +MSLX ; 043x Am486DE2 66 MHz, CPUID +M ; 043x Am486DX4 NV8T +rgmsL ; + ; 0440 i486SL A 25-33 MHz +RmgSL ; + ; 0441 i486SL ?? +Rmg ; + ; 044x i486SL ?? 8K L1, CPUID, With chipset +GMPSX ; M says CPUID from step 3 + ; R says 44xx from OMCU + ; 044x i486DXL ?? 8K L1 +P ; 044x MediaGX (Cyrix) any x is 0-7, DL = DIR0, CPUID +GPS ; + ; 045B i486SX2 aC0 SL Enahnced +RSL ; + ; 045x i486SX2 A Overdrive, CPUID +Rmg ; 045x i486SX2 any 50-66 MHz, 8K L1, CPUID +rMGPX ; M says no CPUID + ; 045x UMC U486SX2 any CPUID +RL ; + ; 0470 i486DX2WB any 0470 on CPUID if WB (see 436) +RGSL ; stepping needs a reset +S ; + ; 0474 Am486DX2-66 x2 ?? WB Mode, CPUID +GMsC ; 0474 Am486DX4 x2 ?? SV8B, WB mode, CPUID +G ; + ; 047x i486DX2WB P24D, in WB mode +GPSX ; M says CPUID from step 3 + ; 047x Am486DX2 ?? WB Mode, 66-100 MHz, CPUID +GMSLX ; + ; 0480 i486DX4 A CPUID +GRmsl ; 0480 IBM BL486DX2 A +R ; 0480 Cx486DX2-V 4V version of Cx486DX2 +R ; 0480 TI486DX2 any +R ; + ; 0481 TI486DX4 any +R ; + ; 0483 i486DX4 any WT mode +Rms ; + ; 0484 Am486DX4 x3 any SV8B, WT mode, CPUID +RGMs ; 0484 Am5x86 x3 A WT mode, 150MHz, CPUID +RGM ; + ; 048x i486DX4 "P24C" WT mode, 16K L1, CPUID +GMPSLX ; M says CPUID from step 3 + ; 148x i486DX4 "P24CT" any 75/100 MHz, 16K L1, overdrive +PmSL ; 048x Am486DX4 any SV8B, WT mode +RMSLX ; + ; 0490 i486DX4 any WB mode, CPUID +RPmgsC ; 0490 Cx5x86 2+ reset ID (has CPUID) +RGMs ; + ; 0494 Am486DX4 x3 any SV8B, WB mode, CPUID +RGMsxC ; 0494 Am5x86 x3 A WB mode, 150MHz (?), CPUID +R ; + ; 049x i486DX4WB WB Mode, 75/100/120 MHz, CPUID +GMPSX ; 049x Cx5x86 CPUID +RGS ; + ; 04E4 Am486DX5-133 A WT mode, CPUID +M ; 04E4 Am5x86 x4 A WT mode, 133/160MHz, CPUID +RGMs ; + ; 04Ex Am5x86 x4 any WT mode, CPUID +GPMSLX ; + ; 04F4 Am486DX5-133 A WB mode, CPUID +M ; 04F4 Am5x86 x4 A WB mode, 133/160MHz, CPUID +RGMs ; + ; 04Fx Am5x86 x4 any WB mode, CPUID +GPMSLX ; + ; 1480 i486DX4 A "DX4ODPR" Overdrive, 5V DX4 +R ; + ; 0x2x Cx5x86 rev.0 Stepping 0, all revisions +M ; 1x2x Cx5x86 rev.1 Stepping 1, reset ID +M ; The above are both: + ; DH=DIR1, DL=DIR0 +M ; + ; 84xx IBM 486BLX any 15-33 Hz +GPL ; 84xx IBM 486BLX2 any 30-66 MHz +PgL ; 84xx IBM 486BLX3 A 45-100 MHz +RPgL ; + ; A40x IBM 486SLC A +RP ; + ; A412 IBM 486SLC2 A ? +gM ; + ; A41x IBM 486SLC2 Ax 33-80 MHz +RPL ; A41x IBM 486SLC any 16-25 MHz +G ; + ; A421 IBM 486SLC2 ? ? +G ; + ; A422 IBM 486SLC2 ? ? +GM ; + ; A42x IBM 486SLC2 Bx 33-80 MHz +RGPL ; + ; A439 IBM 486SLC3 ? ? 486DLC3 in 16-bit mode +G ; + ; A43x IBM 486SLC2 ?? +R ; A43x IBM 486SLC3 any +G ; + ; A480 IBM BL486DX2 A 66-80MHz (CPUID) +RPgL ; + ; A4xy IBM 486SLC any x = multiplier, y = revision +PGL ; + ; WT enh = Writeback enhanced in WT mode + ; WB enh = Writeback enhanced in WB mode + ; + ; Some sources imply that SL enhanced all have CPUID + ; + ; + ; 586+ processor signatures (all can be found without a CPU reset): + ; + ; ID Processor Step Comments + ; + ; 0500 Am5k86 (SSA5) E Revision 1 +RGMsC ; + ; 0501 Am5k86 (SSA5) F Revision 2 +RGMsC ; + ; 0504 Nx586 100 MHz (G,P) or 120 MHz (R) +RGPs ; + ; 0506 Nx586 E2/C0 120 MHz (G,P) or 133 MHz (R) +RGPs ; + ; 050x Pentium (P5) Ax FDIV bug, 16K L1, 1993 +RGPSLX ; 050x Am5k86 x1.5 any Model 0, SSA5, PR75/90/100 +RGPSMLX ; 050x Nx586 any +RMSX ; 050x Rise mP6 iDragon 0.25u, PR166-366 +GPS ; + ; 0511 K5 x1.5 Initial version, WA faulty? +rGMsC ; + ; 0512 K5 x1.5 early version, WA faulty? +rGMs ; 0512 Pentium "P5" Sample +S ; + ; 0513 Pentium "P5" B1 FDIV bug, 50-66 MHz +RGPMsL ; + ; 0514 Pentium "P5" B2 FDIV bug, 60/66 MHz +RgP ; 0514 K5 x1.5 improved version, WA fixed +rGMs ; + ; 0515 Pentium "P5" C1 FDIV bug, 60/66 MHz +RGPMSLC ; + ; 0517 Pentium "P5" D1 60/66 MHz +RGPMSLC ; + ; 151A Pentium "P5T" tA0 O/D, Ver. 1, 120/133 MHz (P60/66) +RGPMS ; + ; 051x Pentium (P5) Bx,others FDIV bug, 16K L1, 1993 +RGPMSX ; 051x K5 x1.5 any Model 1, PR120/133, PR + 30% +RGPMSX ; + ; 0521 Pentium B1 FDIV Bug, 75-100 MHz +RGPMSLC ; + ; 0522 Pentium B3 FDIV Bug, 75-100 MHz +RGPMsLC ; + ; 0524 Pentium B5 75-120 MHz +RGPMsL C ; 0524 K5 x1.75 ?? Model 2 (5-1-4 x1.75) +RGMs ; + ; 0525 Pentium C1,C2 P54CQS, 75-133 MHz (?) +RGPMSLC ; 0525 Pentium mA1 P54LM, Mobile, 75/90 MHz +RGMsL ; + ; 0526 Pentium E0 P54CQS, 75-120 MHz +RGPMsC ; + ; 052B Pentium cB1 P54CQS, 120/133 MHz +RGPMS ; 052B Pentium mcB1 P54LM, Mobile, 100/120 MHz +RGPMs ; + ; 052C Pentium cC0 P54CS, 120-200 MHz +RGPMSC ; 052C Pentium mcC0 P54LM, Mobile, 100-150 MHz +RGMs ; 252C Pentium O/D aC0 P54CT, 125-166 MHz, for P75-100 +RGPMsL ; + ; 052x Pentium any P54C and variants, 16K L1 +RGPMSX ; 052x K5 x1.75 any Model 2, PR150/166, PR + 40% +RGMPSX ; 052x Cx6x86 Early models, see DIR0 +RGPMS ; 052x Rise mP6 iDragon 0.18u, PR333-433 +GPSM ; + ; 0530 Cx6x86 x1,S For revision, read DIR1 +RM ; IBM266x86 100-133 MHz +P ; + ; 1531 Pentium O/D B1,B2 P24CT, Ver. 1.x, 63 MHz for 486 +RGPMsLx ; 0531 Cx6x86 x2,S For revision, read DIR1 +RM ; + ; 1532 Pentium O/D C0 P24CT, Ver. 2.x, 63/83 MHz for 486 +RGPMsLx ; 0532 Cx6x86 x1,P For revision, read DIR1 +RM ; + ; 0533 Cx6x86 x2,P For revision, read DIR1 +RM ; + ; 0534 K5 x2 ?? 5-1-4 x2 +GMs ; 0534 Cx6x86 x4,S For revision, read DIR1 +RM ; + ; 0535 Cx6x86 x3,S For revision, read DIR1 +RM ; + ; 0536 Cx6x86 x4,P For revision, read DIR1 +RM ; + ; 0537 Cx6x86 x3,P For revision, read DIR1 +RM ; + ; 053x K5 x2 any Model 3, PR200, PR + 50% +RGMPSX ; 053x Cx6x86L any See DIRs for revision +RPM ; + ; 0540 IDT Winchip C6 any +gRs ; IDT Winchip C6 0 Some errors +GsM ; + ; 0541 Pentium MMX A1 P55C +Rg ; 0541 IDT Winchip 1 less errors +GsM ; + ; 0542 Pentium MMX A2 +Rgs ; + ; 0543 Pentium MMX xB1 166-233 MHz +RGPMS ; 0543 Pentium MMX mxB1 Mobile, 120-200 MHz +RGPMs ; 1543 Pentium MMX oxB1 P55CT, 180/200 MHz, O/D for P54 +PgMs ; 0543 Crusoe TM5400 500-677 MHz, 64+64K L1, 256K L2 +P ; + ; 0544 Pentium MMX xA3 150-200 MHz, 32K L1 +RGPMs ; 0544 Pentium MMX mxA3 Mobile, 150/166 MHz, 32K L1 +RGPMs ; 1544 Pentium MMX oxA3 P55CT, 125-166 MHz O/D, for P54 +RGPMs ; + ; 054x Pentium MMX any P55C and variants, 32K L1 +X ; 054x Cyrix MediaGX any GXi, GXm, x is 0-7, DL = DIR0 +RMPG ; 054x IDT Winchip C6 any MMX, 180-240MHz +rGPSMX ; 054x Crusoe any Transmeta Crusoe TM3x00 and TM5x00 +gS ; + ; 155x Pentium MMX P55C Overdrive for 486DX4 +GMP ; + ; 0561 K6 Rev. B +RGMs ; + ; 0562 K6 Rev. C +rGMs ; + ; 156x Pentium MMX P54CTB, 100-200 MHz, O/D for P54C +GP ; 056x K6 Model 6, 166-266 MHz +RGPMSX ; + ; 0570 Pentium mA4 Mobile, 75-100 MHz +RGPMs ; 0570 K6 Rev. A +rGMs ; + ; 057x Pentium ?? P54LM, Mobile, P says it's P54C +PGSX ; 057x K6 Model 7, 166-300 MHz +RGPMSX ; 057x K6M Mobile +rGPs ; 057x K6E Embedded +rGPMs ; + ; 0580 K6-2 Rev. A +rGMPs ; 0580-5 IDT Winchip 2 200-240 MHz +GPsm ; + ; 0581 Pentium MMX myA0 Mobile, 166-266 MHz +RGPMs ; + ; 0582 Pentium MMX myB2 Mobile, 266/300 MHz +PMs ; + ; 0584(?) Pentium MMX mobile, MMX bug +Ps ; + ; 0587-9 IDT Winchip 2A 2A 200-233 MHz +GPsm ; + ; 058A-F IDT Winchip 2B 2B 233-250 MHz +GPsm ; + ; 058C K6-2 Rev A Model 8, 3D-Now! +CRgMPs ; 058C K6-2M Mobile +rgPs ; 058C K6-2-P-M Mobile, 266-475MHz +rgPs ; 058C K6-2E Embedded +rgPs ; + ; 058x Pentium MMX P55C, Mobile +X ; 058x K6-2(E) any Model 8, 200-550 MHz +RGMPSX ; 058x mP6 iDragon II 0.25u, 256K L2 (Rise) +GP ; 058x IDT Winchip C2 any 64K L1, MMX, 3DNow! (samples only) +GPSMX ; + ; 0591 K6-3 1, Rev B +grMs ; + ; 059x K6-2+ any +RM ; 059x K6-3 any Stepping mask = 0-3 +rGMPSX ; 059x K6-3-P any +rgPs ; 059x K6-3+ any +rgP ; 059x K6-3E+ any Embedded +rgP ; 059x IDT Winchip 3 128K L1 +rGPSM ; 059x mP6 iDragon II 0.18u, PR380-466 (Rise) +rGP ; + ; 05D4 K6-2+ M any Mobile +Ps ; 05D4 K6-2E+ any Embedded +Ps ; + ; 05Dx K6-2+,K6-3+ any [7-4] = K6-2+, [3-0] = K6-3+ +GMS ; + ; 05xx Transmeta Crusoe +G ; + ; P24T = PODP5V63, PODP5V83, Socket 3,6 + ; P5T = PODP5V120, PODP5V133, Socket 4 + ; P54LM = Mobile, Vcc=2.9V + ; P54T = PODP3V125, PODP3V150, PODP3V166, Socket 5,7 + ; + ; + ; 0600 Cx6x86MX x1.0 +gmPs ; + ; 0601 Cx6x86MX x2.0 +gmPs ; + ; 0602 Cx6x86MX x2.5 +gmps ; + ; 0603 Cx6x86MX x3.0 +gmps ; + ; 0604 Cx6x86MX x3.5 +gmps ; + ; 0605 Cx6x86MX x4.0 +gmps ; + ; 0606 Cx6x86MX x4.5 +gmps ; + ; 0607 Cx6x86MX x5.0 +gmps ; + ; 0608 Cx6x86MX x1 +gmps ; + ; 0609 Cx6x86MX x2.0 +gmps ; + ; 060A Cx6x86MX x2.5 +gmps ; + ; 060B Cx6x86MX x3.0 +gmps ; + ; 060C Cx6x86MX x3.5 +gmps ; + ; 060D Cx6x86MX x4.0 +gmps ; + ; 060E Cx6x86MX x4.5 +gmps ; + ; 060F Cx6x86MX x5.0 +gmps ; + ; 060x Pentium Pro A(Sample) P6, 120-133 MHz, 16K L1, 256K L2 +RGPSX ; 060x Pentium Pro P6L, 0K L2 +Ps ; 060x Cx6x86MX any Rev. 1.2 has CPUID bug. +GMPS ; DIR1 has step/revision info + ; + ; 0611 Pentium Pro B0,Sample 150 MHz, 256K L2 +RGPMs ; 0611 Athlon C1 Model 1, Slot A, external L2 +gMPsx ; + ; 0612 Pentium Pro C0 150 MHz, 256K L2 +RGPMs ; 0612 Athlon C2 Model 1, Slot A, external L2 +gMPsx ; + ; 0616 Pentium Pro sA0 180/200 MHz, 256K L2 +RGPMs ; + ; 0617 Pentium Pro sA1 166-200 MHz, 256K/512K L2 +RGPMs ; + ; 0619 Pentium Pro sB1 166-200 MHz, 256K/512K/1M L2 +RGPMs ; 1619 PII O/D ?? P6T, 300-333 MHz, PII O/D for P6 +Ps ; + ; 061x Pentium Pro any P6, 256K/512k/1M L2 +rgpmSX ; + ; 0621 Athlon A1 Model 2, Slot A, external L2 +gMPs ; + ; 0622 Athlon A2 Model 2, Slot A, external L2 +gMPs ; + ; 0630 Duron A0 Model 3, CPUID cache error +GMPs ; + ; 0631 Duron A2 Model 3, no CPUID cache error +GMPs ; + ; 0632 PII ? 233-333 MHz +Pgs ; 1632 PII O/D tdB0 Overdrive for PPro +RGs ; + ; 0633 PII C0 233-333 MHz +RGPMs ; + ; 0634 PII C1 233-333 MHz +RGPMs ; + ; 063x PII "Klamath" any 512M cacheable, 32K L1, 512K L2 +RGMPSX ; 163x PII O/D P6T, Overdrive for Socket 8 +Rs ; + ; 0642 Athlon A4-A7 +GMPs ; + ; 0643 Athlon B0 +GPs ; + ; 0644 Athlon A9 +gMPs ; + ; 064x Athlon Thunderbird, Model 4 +gMPs ; 164x Pentium Pro ?? P55CT, PII Overdrive for PPro +GP ; + ; 0650 PII dA0 266/333 MHz +RGPMs ; 0650 PII mdA0 Mobile, 233/266 MHz, 512k L2 +RPMs ; 0650 PII mmdA0 Mobile, 233/266 MHz, 512k L2 +RPMs ; 0650 Celeron dA0 266/300 MHz, 0k +RGPMs ; + ; 0651 PII dA1 300-400 MHz +RGPMs ; 0651 Celeron dA1 266/300 MHz, 0k +RGPMs ; + ; 0652 PII dB0 266-450 MHz +RGPMs ; 0652 PII mdB0 Mobile, 233-300 MHz, 512k L2 +RPMs ; 0652 PII mmdB0 Mobile, 233-300 MHz, 512k L2 +RPMs ; 0652 PII TdB0 Overdrive, 333 MHz +Ms ; 0652 PII Xeon B0 400 MHz, 512K/1M L2 +RGMs ; 0652 Celeron dB0 266/300 MHz, 0k +RGPMs ; + ; 0653 PII dB1 350/400 MHz +gMs ; 0653 PII Xeon B1 400/450 MHz, 512K/1/2M L2 +RgMs ; + ; 065x PII "Deschutes" 266+ MHz, 512K L2, 4G cachable +GPMSX ; 065x PII "Tonga" Mobile, 233-300 MHz, 0K L2 +Ps ??? ; 065x PII Xeon +GPMs ; 065x Celeron "Covington" 266, 300 MHz, 0K L2 +GPMs ; 065x Cx6x86MX If DIR1 is 08h to 07Fh, it's an MII +RMS ; Check DIR1 for steppings etc. + ; 065x VIA Cyrix III any "Joshua". unverified +G ; + ; 0660 Celeron mA0 300-433 MHz +RGPMs ; 0660 PII PE mA0 256k L2 +RGs ; 0660 Athlon A0 Model 6 +MPs ; 0660 Athlon Mobile +Ps ; 0660 VIA CIII Samuel 128K L1, 400-750 MHz +gPms ; + ; 0661 Athlon A2 Model 6 +MPs ; 0661 Athlon Mobile +MPs ; + ; 0662 Athlon A5 Model 6 +MPs ; 0662 Athlon Mobile +MPs ; 0662 Athlon MP Dual CPU +MPs ; 0662 Athlon XP +MPs ; + ; 0665 Celeron mB0 300-533 MHz +gMs ; + ; 066A Celeron mcbA0, Mobile, 233-466 MHz +gMs ; mcpA0, Mobile, 266-466 MHz +gMs ; cmmA0 Mobile, 266-466 MHz +gMs ; 066A PII PE md[xbp]A0, Mobile, 266-400 MHz +gMs ; mq[bp]A1 Mobile, 400 MHz +gMs ; 066A PII PE dmmA0 Mobile, 266-400 MHz +gMs ; + ; 066x PII PE Mobile, 256K L2 +GSX ; 066x Celeron Mendocino, 128K L2 +RGPMs ; 066x Athlon +M ; 066x VIA Cyrix III Samuel Winchip C5A, 450-800 MHz? +GPMS ; + ; 0670 Duron 1 GHz +, Camaro, Morgan +Psm ; 0670 Duron 1 GHz +, Thoroughbred +Psm ; 0670 Duron 1 GHz +, Appaloosa, Dual CPU +Psm ; + ; 0670-7 VIA C3 Samuel II Winchip C5B, 666-733 MHz +PMS ; 0670-7 VIA Eden ESP Samuel 2, 4x100 MHz +PMs ; + ; 0672 PIII kB0 450/500 Hz +gPMs ; 0672 PIII Xeon B0 500 MHz +gMs ; + ; 0673 PIII kC0 450-600 Hz +gPMs ; 0673 PIII Xeon C0 500/550 MHz +gMs ; + ; 0678-F VIA C3 Ezra Winchip C5C, 800-933 MHz +PMS ; 0678-F VIA Eden ESP Ezra, 4x133 MHz +PMs ; + ; 067x PIII "Katmai" 512K L2 +GMSX ; 067x PIII Xeon B0 512/1024/2048K L2 +gMs ; 067x Duron +psM ; 067x VIA C3/Eden 128K L1, 64K L2 +P ; + ; 0680-7 VIA C3 Ezra-T Winchip C5C, 800-933 MHz +PM ; 0680-7 VIA Eden ESP Ezra-T, 5x133 MHz +PM ; + ; 0681 PIII cA2 500-800 MHz +gPMs ; 0681 PIII BA2,PA2,MA2 Mobile, 400-650 MHz +gPMs ; 0681 PIII Xeon A2 600-800 MHz +gMs ; 0681 Celeron BA2,PA2 Mobile, 400-500 MHz +gMs ; 0681 Celeron MA2 Mobile, 450/500 MHz +gMs ; + ; 0683 PIII cB0 500 MHz - 1.0 GHz +gPMS ; 0683 PIII BB0,PB0,MB0 Mobile, 400-750 MHz +gPMs ; 0683 PIII Xeon B0 600-933 MHz +gMs ; 0683 Celeron cB0 533-700 MHz +gMs ; 0683 Celeron BB0,PB0 Mobile, 400-650 MHz +gMs ; 0683 Celeron MB0 Mobile, 450-650 MHz +gMs ; + ; 0686 PIII cC0 600 MHz - 1.13 GHz +gPMS ; 0686 PIII BC0,PC0,MC0 Mobile, 400-900 MHz +gPMS ; 0686 PIII Xeon C0 733 MHz - 1.0 GHz +gMs ; 0686 Celeron C0 566-850 MHz +gMs ; 0686 Celeron BC0,PC0 Mobile, 400-750 MHz +gMs ; 0686 Celeron MC0 Mobile, 450-700 MHz +gMs ; + ; 068A PIII D0 600 MHz - 1.13 GHz +PMS ; 068A PIII BD0,PD0 Mobile, 500-1000 MHz +PMs ; 068A PIII (U)LV D0 Mobile, 500+ MHz +Ps ; 068A Celeron D0 733 MHz - 1.1 GHz +Ms ; 068A Celeron BD0,PD0 Mobile, 500-850 MHz +Ms ; 068A Celeron FBD0,FPD0 Mobile, 733-933 MHz +Ms ; + ; 068x PIII "Coppermine" 256K L2 +GMSX ; 068x PIII Xeon "Coppermine" 800+ MHz, 256K L2 +gMs ; 068x Celeron "Coppermine" 128K L2, W/SSE +GPMs ; 068x VIA Eden 128K L1, 64K L2 +Pm ; + ; 06A0 PIII Xeon A0 Cascades, 700 MHz +gMsx ; + ; 06A1 PIII Xeon A1 Cascades, 700 MHz +gPMsx ; + ; 06A4 PIII Xeon B0 Cascades, 700/900 MHz +gPMsx ; + ; 06Ax PIII Xeon Gallatin?? 1024/2048K L2 +GPMS ; + ; 06B1 PIII tA1 1.0-1.4 GHz +PMs ; 06B1 PIII-M FPA1,FBA1 Mobile, 700-1200 MHz +PMs ; 06B1 Celeron tA1 Tualatin, 1.0-1.3 GHz +PMs ; 06B1 Celeron FBA1 Tualatin, Mobile, 650-1200 MHz +PMs ; 06B1 Celeron FPA1 Tualatin, Mobile, 1066-1200 MHz +PMs ; + ; 06Bx PIII any Tualatin" 256/512K L2 +PMS ; 06Bx PIII-M any Tualatin, 512K L2 +PMs ; 06Bx Celeron any Tualatin, 256K L2 +PMs ; + ; 0F01-4 Pentium 4 1.0 GHz, 16K L1 +Ps ; + ; 0F07 Pentium 4 B2 1.3-1.5 GHz +Ps ; + ; 0F0A Pentium 4 C1 1.3-1.8 GHz +PMs ; 0F0A Pentium 4 Xeon C1 1.4-1.7 GHz +PMs ; + ; 0F11 Pentium 4 Xeon C0 MP, 1.4-1.6 GHz +M ; + ; 0F12 Pentium 4 D0 1.4-2.0 GHz +PMs ; 0F12 Pentium 4 Xeon D0 1.5-2.0 GHz +PMs ; + ; 0F13 Pentium 4 E0 1.6-2.0 GHz +M ; + ; 0F0x-1x Pentium 4 Bx-Dx Willamette, (P: 8+12K L1?), 256K L2 +PMS ; 0F0x-1x P4 Xeon Bx-Dx Foster, As Willamette +PMS ; + ; 0F24 Pentium 4 B0 1.6-2.53 GHz +Ms ; 0F24 Pentium 4 B0 Mobile, 1.6-1.7 GHz +Ms ; 0F24 Pentium 4 Xeon B0 1.8-2.4 GHz +PMs ; + ; 0F2x Pentium 4 Northwood, 512K L2 +MS ; 0F2x P4 Xeon Prestonia, As Northwood +MS ; + ; + ; + ; 0Fxx Pentium 4 Prescott, integrated Northbridge +P ; 1.6+ GHz, single/dual RDRAM + ; 0Fxx Pentium 4 Nocona ??? +P ; 0Fxx Pentium 4 any +GP ; 0Fxx P4 Celeron any 1.8+ GHz, 8+12K L1, 128K L2 +P ; + ; + ; + ;-------------------------------------------------------------------------------+ ; + ; Contents of Debug Registers (in real mode) + ; + ; DR6 OR- 1 DR6 AND 0 DR7 OR -1 DR7 AND 0 Processor + ; + ; 0x0000E00F 0x00000000 0xFFFF23FF 0x00000000 i386xx, i486xx + May use DR7[15,14,12] ? ; Am386xx, Am486xx + ; + ; 0xFFFF01FF 0x00000000 Enhanced Am486xx + ; + ; 0xFFFFFFFF 0xFFFF1FF0 0xFFFF27FF 0x00000400 Pentium + May use DR7[15,14,12] ? ; + ; 0xFFFFCFFF 0xFFFF0FF0 0xFFFF27FF 0x00000400 Cx486DX + DR7 also on cx486DX2/4 ; TI468SXLC/SLC(e) + ; + ; 0xFFFFEFFF 0xFFFF2FF0 0xFFFF23FF 0x00000000 Cx486SLC, TI486SXL + ; + ; 0x0000F00F 0x00000000 0xFFFFFBFF 0x00000000 IBM 486SLC2 + ; + ; 0x0000E00F 0x00000000 0xFFFF13FF 0x00000000 Am486SXLV + ; Am386SXLV/DXLV + ; + ; 0x0000CFFF 0x00000FF0 0xFFFF27FF 0x00000400 Cx6x86, Cx6x86MX + ; + ;-------------------------------------------------------------------------------+ ; + ; Flag tests: + ; + ; Not only Cyrix can be detected by testing the behaviour of flags. + ; + ; The standard test to differentiate Cyrix from other processors is the DIV + ; test, checking whether any flags have changed after the div. + ; + ; Other tests can help differentiate between some processor cores. + ; + ; Known processor cores (386 and later only): + ; + ; Processor Comment Source + ; + ; 386 (vendors aren't all the same) R + ; Cx486SLC/Cx486DX (and clones, like TI486SXL) R + ; i486 R + ; UMC U5S R + ; Cyrix Cx5x86 (M1sc) R + ; Pentium R + ; NexGen Nx5x86 R + ; Cyrix Cx6x86 (M1) R + ; AMD Am5k86 R + ; Pentium Pro R + ; + ; What sort of tests to perform? + ; + ; MUL + ; DIV + ; IMUL + ; IDIV + ; NEG (ZF) + ; AND/OR/XOR/etc (AF) + ; Shift/Rotates (OF) + ; + ; and more (details when I do my own tests). + ; + ; How to test each instruction: + ; + ; xor ah,ah + ; sahf + ; ; insert test sequence + ; lahf + ; mov bh,ah + ; + ; xor ah,ah + ; dec ah + ; sahf + ; ; insert test sequence + ; lahf + ; + ; ; analyse the results to see what flags were changed by which instruction, + ; ; and under what circumstances. + ; + ; Test sequences recorded in RBIL are: + ; + ; MUL: mov ax,0000h + ; mov bx,1234h + ; mul bx + ; + ; DIV: mov ax,1234h + ; mov bl,22h + ; div bl + ; + ; IMUL: mov ax,0092h + ; mov bl,22h + ; imul bl + ; + ; IDIV: mov ax,0ffeeh + ; mov bl,22h + ; idiv bl + ; + ; LOG: mov ax,0ff00h + ; mov bx,0f0fh + ; and ax,bx + ; + ; Flags recorded in RBIL as changing: + ; + ;CPU ------------- Sequence ------------- + ;CORE MUL DIV IMUL IDIV LOG Note + ; ------------------------------------------------------------------------ + ;286 ALL ALL ALL ALL ALL as 386,i486 + ; DRIVEN DRIVEN DRIVEN DRIVEN DRIVEN + ; ------------------------------------------------------------------------ + ;386 ALL ALL ALL ALL ALL as 286,i486 + ; DRIVEN DRIVEN DRIVEN DRIVEN DRIVEN + ; ------------------------------------------------------------------------ + ;i486 ALL ALL ALL ALL ALL as 286,386 + ; DRIVEN DRIVEN DRIVEN DRIVEN DRIVEN + ; ------------------------------------------------------------------------ + ;Cx486SLC ZSPA ALL ZSPA ALL AF + ; PASSED PASSED PASSED PASSED PASSED + ; ------------------------------------------------------------------------ + ;UMC U5S ZSPA ALL ZSPA ALL ALL + ; PASSED PASSED PASSED PASSED DRIVEN + ; ------------------------------------------------------------------------ + ;Cx5x86 PA COPA PA COPA ALL + ; PASSED PASSED PASSED PASSED DRIVEN + ; ------------------------------------------------------------------------ + ;Pentium ZSPA ALL ZSPA ALL ALL as Pentium Pro + ; PASSED DRIVEN PASSED DRIVEN DRIVEN + ; ------------------------------------------------------------------------ + ;Nx5x86 ???? ???? ???? ???? ???? Not yet known + ; ???? ???? ???? ???? ???? + ; ------------------------------------------------------------------------- + ;Cx6x86 ALL C,O ALL C,O ALL + ; DRIVEN PASSED DRIVEN PASSED DRIVEN + ; ------------------------------------------------------------------------ + ;Am5k86 ZSPA CO ZSPA CO ALL + ; PASSED PASSED PASSED PASSED DRIVEN + ; ------------------------------------------------------------------------ + ;Pentium Pro ZSPA ALL ZSPA ALL ALL as Pentium + ; PASSED DRIVEN PASSED DRIVEN DRIVEN + ; + ;-------------------------------------------------------------------------------+ ; + ; Instructions that are only valid on a small range of processors. + ; + ; CMPXCHG 0F A6 /r 486 Step A CMPXCHG486 rm8,reg8 + ; 0F A7 /r 486 Step A CMPXCHG486 rm16,reg16 + ; CMPXCHG486 rm32,reg32 + ; + ; F4X4 DB F1 IIT x87 Multiply vector by 4x4 matrix + ; FNSTDW DF E1 i387SL Mobile Store Device Word Register, no wait + ; FNSTSG DF E2 i387SL Mobile Store Signature Word Register, no wait + ; FRICHOP DD FC Cx FPUs to 486 Round to Integer, chop fractional part + ; FRINEAR DF FC Cx FPUs to 486 Round to Nearest Integer + ; FRINT2 DB FC Cx FPUs to 486 Round to Integer, if fractional is 0.5 + ; rounds absolute to infinity + ; FRSTPM DB E5 i287XL/XLT FPU Reset Pmode + ; FSBP0 DB E8 IIT x87 Set Bank Pointer to Bank #0 + ; FSBP1 DB EB IIT x87 Set Bank Pointer to Bank #1 + ; FSBP2 DB EA IIT x87 Set Bank Pointer to Bank #2 + ; + ; IBTS 0F A7 /r i386 Step A0-B0 Insert Bit String + ; XBTS 0F A6 /r i386 Step A0-B0 Extract Bit String + ; + ; RDMSR 0F 32 IBM 386SLC Read MSR, this works the same as for + ; 486SLC/2/3 Pentium processors. + ; WRMSR 0F 30 IBM 486SLC2 Write MSR, works same as for Pentium + ; + ; RSDC 0F 79 /r Cx486S/S2/D/D2 Restore Register and Descriptor. + ; Cx486DX/DX2/DX4 + ; IBM BL486DX/DX2 + ; TI486SLC/DLC/e + ; TI486SXL/2/C + ; TI Potomac + ; RSLDT 0F 7B /0 as for RSDC Restore LDTR and Descriptor + ; RSTS 0F 7D /0 as for RSDC Restore TR and Descript. + ; SVDC 0F 78 /r as for SVDC Save Register and Descriptor + ; SVDLDT 0F 7A /0 as for SVDC Save LDTR and Descriptor + ; SVTS 0F 7C /0 as for SVDC Save TR and Descriptor + ; + ; + ; SMINT 0F 7E Cx486DX/DX2/DX4 Save CPU State and enter SMM + ; IBM BL486DX/DX2 + ; never in Cx486S/S2/D/D2 + ; never in any TI chips + ; + ; UMOV 0F 10-13 /r Am386SXLV/DXLV Mov Data to Main (User) Memory + ; AMD 486s Valid in SMM and non-SMM modes + ; IBM 486SLC2 #UD if SMM not supported + ; All SL/SMM enhanced + ; + ;-------------------------------------------------------------------------------+ ; + ; Some instructions with known bugs. + ; + ; This list is not intended to be complete. For a complete listing, + ; refer to the file 86BUGS.LST, distributed with Ralf Brown's + ; Interrupt List. + ; + ; BSWAP 0F C8+r 486 Swap byte order in 32-bit register. + ; Faulty on many 486s when in 16-bit with no 0x66 + ; prefix or 32-bit mode with the prefix. + ; + ; FDIV Various 486 On some 486, the FDIV instructions will + ; incorrectly accept a register operand + ; that has been tagged as empty but holds + ; a non-zero value, when there is another + ; FP instruction within 35 FPU clock + ; cycles. When that happens, the FDIV + ; will use the invalid value, and the + ; following instruction will also + ; generate an invalid result. + ; + ; FLDENV D9 /4 387 On some 387s, if the last two bytes of the + ; environment can't be read (whatever the + ; reason), the instruction can't be + ; restarted. + ; A workaround is to make sure the environment+ ; is 128-byte aligned, or to read it + ; before executing the instruction. + ; + ; FPTAN D9 F2 486 On some 486s, a specific set of code, when + ; executed on a specific set of data, + ; will corrupt the FPU stack, without + ; signalling the FPU or CPU. + ; A workaround is to follow FPTAN with FCLEX, + ; FINIT, FLDCW, FSTSW, FSTSWAX, + ; or or by a WAIT and a non-FPU + ; instruction + ; + ; FRSTOR DD /4 387 This bug is the same as that for FLDENV. + ; + ; FSAVE 9B /6 386/7 On some 386s, an incorrect opcode is saved when + ; FNSAVE DD /6 386/7 in real or V86 mode. The right address + ; is saved, and can be used to retrieve + ; the opcode. + ; On some 387's, the same bug as for FLDENV is + ; present. + ; + ; FSCALE D9 FD 486 On some 486s, if -1 zero after REP INS. + ; 486 Early 486 may hang when the destination address + ; spans a dword boundary. + ; + ; INVD 0F 08 486 On some 486s, if a cache line fill is in + ; progress at the same time an INVD is + ; being executed, the line is moved into + ; the cache and not invalidated. + ; Always disable the cache prior to an INVD + ; on a 486. + ; + ; LAR 0F 02 /r 386 On some 386s, this will incorrectly allow + ; access to selector 0 in the GDT. + ; A workaround is to have selector 0 as a + ; NULL descriptor, which cause LAR to + ; execute correctly. + ; + ; LSL 0F 03 /r 386 The first bug is the same as for LAR. + ; On some 386s, if LSL is immediately followed + ; by an instruction that uses the stack, + ; (E)SP will be corrupted. + ; + ; MOVS A4/A5 386 On some 386s, MOVS followed by an instruction + ; with a different address size will + ; result in the wrong destination + ; register being updated. + ; This means that in some cases DI will be + ; updated instead of EDI, or vice-versa. + ; REP MOVS will additionally update (E)SI + ; when this bug is present. + ; + ; MUL F7 /4 386 On some 386s, there is a bug in the 32-bit + ; multiply. In processors with this bug, + ; the high word of the result that should + ; be in EAX is left in DX, and the dword + ; that should be in EDX is left in EAX. I + ; have no more info on what is left in + ; the high word of EDX. + ; Some 386s also have a bug in 16-bit multiplies. + ; I have no more information on this. + ; + ; POPA 61 386 On some 386s, POPA followed by any instruction + ; which uses an EA that has a base + ; register and an index register, where + ; the index isn't (E)AX, EAX will be + ; corrupted. + ; + ; VERR 0F 00 /4 386 These instruction will incorrectly allow a NULL + ; VERW 0F 00 /5 386 selector to be specified on some 386s. + ; + ; WBINVD 0F 0D 486 This has the same bug as INVD. + ; + ; + ;-------------------------------------------------------------------------------+ ;-------------------------------------------------------------------------------+ ; + ; Acknowledgements: + ; + ; The following sources of information were used when developing this code. + ; + ; Source code: + ; + ; CPUID.ZIP Copyright Robert Collins ([email protected]) + ; mostly used to help write code to detect possibility of + ; obtaining a reset signature. + ; The package is available on www.x86.org + ; + ; CYRIXID.ZIP Author unknown + ; Useful for some info on Cyrix ID register values. + ; + ; CPU117.ZIP Copyright Bobby Z and other contributors + ; This is version 1.17 ot the TMi0SDGL(tm) package. + ; This is a useful reference source for identification + ; routines, and has some stepping info. + ; + ; Documentation: + ; + ; Am386 SX/SXL/SXLV Embedded processor Manual 20037.PDF AMD + ; + ; Am486DX/DX2 Hardware Reference Manual 17965.PDF AMD + ; Am486 Microprocessor Software Users Manual 18497.PDF AMD + ; Am486DX4 Microprocessor Datasheet 19160.PDF AMD + ; Am486DX2 Microprocessor Datasheet 19200.PDF AMD + ; Enhanced Am486 Microprocessor Family Manual 19225.PDF AMD + ; Am5x86 Microprocessor Family Manual 18751.PDF AMD + ; Am486DE2 Embedded Microprocessor Manual 20037.PDF AMD + ; Enhanced Am486DX Microprocessor Family Manual 20736.PDF AMD + ; + ; AMD K5 Processor Datasheet 18522.PDF AMD + ; AMD 5K86 Processor Technical Reference Manual 18524.PDF AMD + ; AMD-K5 Processor Software Development Guide 20007.PDF AMD + ; + ; AMD-K6 Processor Datasheet 20695.PDF AMD + ; AMD-K6 MMX Enhanced Processor Manual 20726.PDF AMD + ; Mobile AMD-K6 Processor Data Sheet 21049.PDF AMD + ; AMD-K6 Processor Revision Guide Model 6 21266.PDF AMD + ; AMD-K6 Processor Revision Guide Model 7 21846.PDF AMD + ; + ; AMD-K6-2 Processor Revision Guide Model 8 21641.PDF AMD + ; AMD-K6-2 Processor Data Sheet 21850.PDF AMD + ; Mobile AMD-K6-2 Processor Data Sheet 21896.PDF AMD + ; AMD-K6-2E Processor Data Sheet 22529.PDF AMD + ; Mobile AMD-K6-2+ Processor Data Sheet 23446.PDF AMD + ; AMD-K6-2E+ Embedded Processor Data Sheet 23542.PDF AMD + ; + ; AMD-K6-III Processor Data Sheet 21918.PDF AMD + ; AMD-K6-III Processor Revision Guide - Model 9 22473.PDF AMD + ; Mobile AMD-K6-III-P Processor Data Sheet 22655.PDF AMD + ; Mobile AMD-K6-III+ Processor Data Sheet 23535.PDF AMD + ; AMD-K6-III+ Embedded Processor Data Sheet 23543.PDF AMD + ; + ; AMD Athlon Processor Model 1/2 Revision Guide 22557.PDF AMD + ; AMD Athlon Processor Model 4 Revision Guide 23614.PDF AMD + ; AMD Athlon Processor Model 6 Revision Guide 24332.PDF AMD + ; + ; AMD Duron Processor Model 3 Revision Guide 23865.PDF AMD + ; + ; AMD Processor Recognition Application Note 20734.PDF AMD + ; AMD Processor Recognition Code Sample 21035.PDF AMD + ; + ; + ; IDT Winchip C6 Processor Datasheet Centaur + ; IDT Winchip C6 Processor Family BIOS Writers Guide Centaur + ; + ; IDT Winchip 2 Processor Data Sheet Centaur + ; IDT Winchip 2A Processor Data Sheet Centaur + ; IDT Winchip 2B Processor Data Sheet Centaur + ; + ; IDT Winchip 3 Processor Data Sheet Centaur + ; + ; IDT Winchip Processor Family BIOS Writers Guide ver 4 Centaur + ; + ; + ; 5x86 CPU BIOS Writers Guide Revision 1.1 Cyrix + ; + ; 6x86 Processor Data Sheet Cyrix + ; 6x86L Processor Data Sheet Cyrix + ; + ; Cyrix MII Data Book Cyrix + ; + ; Cyrix MediaGX Data Book Cyrix + ; + ; Cyrix CPU Detection Guide Cyrix + ; + ; + ; IBM 6x86MX Microprocessor Databook IBM + ; IBM 6x86MX Microprocessor BIOS Writers Guide IBM + ; + ; + ; INTEL 80386 PROGRAMMER'S REFERENCE MANUAL Intel + ; Intel386 DX Microprocessor Data Sheet 23163011.PDF Intel + ; Intel386 DX Processor Specification Update 27287402.PDF Intel + ; Intel386 SX Microprocessor Data Sheet 24028708.PDF Intel + ; Intel386 DX Processor Specification Update 27287402.PDF Intel + ; Intel386 CXSA Embedded Microprocessor Datasheet 27241803.PDF Intel + ; Intel386 SXSA Embedded Microprocessor Datasheet 27241903.PDF Intel + ; Intel386 EX Embedded Microprocessor Datasheet 27242004.PDF Intel + ; Intel386 EX Microprocessor User's manual 27248502.PDF Intel + ; Intel386 CX/SXSA Processor Specification Update 27286902.PDF Intel + ; Intel386 EX Processor Specification Update 27287310.PDF Intel + ; + ; Military i486 Processor Family Data Sheet 27132903.PDF Intel + ; Embedded ULP i486 SX Processor Data Sheet 27273102.PDF Intel + ; Embedded ULP i486 GX Processor Data Sheet 27275502.PDF Intel + ; Embedded i486 SX Processor Data Sheet 27276903.PDF Intel + ; Embedded i486 DX2 Processor Data Sheet 27277002.PDF Intel + ; Embedded i486 DX4 WB Processor Data Sheet 27277102.PDF Intel + ; Embedded i486 Family Developers Manual 27302101.PDF Intel + ; + ; Pentium Processor Specification Update 24248041.PDF Intel + ; 60- and 66-MHz Pentium Processor Spec Update 24332601.PDF Intel + ; Pentium Pro Processor Specification Update 24268935.PDF Intel + ; Pentium II Processor Specification Update 24333746.PDF Intel + ; Mobile Pentium II Processor Spec. Update 24388737.PDF Intel + ; Pentium II Xeon Processor Specification Update 24377632.PDF Intel + ; Pentium III Processor Specification Update 24445339.PDF Intel + ; Pentium III Xeon Processor Specification Update 24446032.PDF Intel + ; Mobile Pentium III Processor Spec. Update 24530628.PDF Intel + ; Pentium 4 Processor Specification Update 24919921.PDF Intel + ; Mobile Pentium 4 Processor-M Spec. Update 25072101.PDF Intel + ; Intel Xeon Processor Specification Update 24967812.PDF Intel + ; + ; Intel Processor I/D and the CPUID Instruction 24161819.PDF Intel + ; P 4 Processor I/D and the CPUID Instruction Intel + ; + ; + ; Geode GXm Processor Datasheet GXM.PDF NSC + ; Geode GXLV Processor Series Datasheet GXLV.PDF NSC + ; Geode GX1 Processor Series Datasheet GX1.PDF NSC + ; + ; iDragon MP6 IA Processor Datasheet Rise + ; iDragon MP6 IA Processor BIOS Writers Guide Rise + ; + ; VIA Cyrix III Processor Datasheet VIA + ; VIA C3 Samuel 2 Processor Datasheet VIA + ; VIA C3 Ezra Processor Datasheet VIA + ; VIA C3 Ezra-T Processor Datasheet VIA + ; VIA C3 in EBGA Datasheet VIA + ; VIA Eden Embedded System Platform Processor Datasheet VIA + ; + ; + ; cyrixcpu.txt Christian Ludloff + ; 80x86.cpu ditto + ; + ; Ralf Brown's Interrupt List + ; + ; Websites: + ; + ; http://www.sandpile.org/ + ; http://grafi.ii.pw.edu.pl/gbm/x86/ + ; http://www.plasma-online.de/ + ; + ; People: + ; + ; The following individuals also provided me with some of the information + ; in this document: + ; + ; Norbert Juffa + ; H. Peter Anvin + ; + ; + ; Thanks also to the many other authors whose sites I visited before I started + ; recording my work. + ; + ;-------------------------------------------------------------------------------+